CMOS Technology

Paulo Moreira &

Jorgen Christiansen
CERN - Geneva, Switzerland

This part is compressed set of transparencies

from Paulo Moreira:
http://paulo.moreira.free.fr/

Paulo Moreira CMOS technology 1

 Outline

• Part 1: Basic CMOS technology (from Paulo

Moreira)
– How it all started
– CMOS Transistors
– Parasitics
– The CMOS inverter
– Technology
– Scaling

Paulo Moreira CMOS technology 2

 Introduction
1906 Audion (Triode), 1906 1947 First point contact transistor (germanium), 1947
1947
1906 Lee De Forest
John Bardeen and Walter Brattain
Bell Laboratories

First integrated circuit (germanium), 1958

Intel Pentium II, 1997
1958
1958 Jack S. Kilby, Texas Instruments
1997 Gate Length: 0.35, Clock: 233MHz
transistors resistors and capacitors 1997 Number of transistors: 7.5 M

Paulo Moreira CMOS technology 3

 The world is becoming digital
• Digital processing is taking over:
– Computing, DSP
– Instrumentation
– Control systems
– Telecommunications
– Consumer electronics
• But analog is still needed in critical parts:
– Amplification of weak signals
– A/D and D/A conversion
– Radio Frequency (RF) communications
• As digital systems become faster and circuit densities
increase the analog side of digital circuits are
becoming important
– Crosstalk, Delays in R-C wires, Jitter, matching, substrate
noise, etc.

Paulo Moreira CMOS technology 4

 “Moore’s Law”
42 M transistors

Number of transistors doubles every 2.3 years

(acceleration over the last 4 years: 1.5 years)

Increase: ~20K

2.25 K
transistors

(From: http://www.intel.com)

“Integration complexity doubles every three years”

Gordon Moore, Fairchild1965

Paulo Moreira CMOS technology 5

 Trends

Paulo Moreira CMOS technology 6

 Driving force: Economics
• Traditionally, the cost/function in an IC is reduced by
25% to 30% a year.
• To achieve this, the number of functions/IC has to be
increased. This demands for:
– Increase of the transistor count
– Decrease of the feature size (contains the
area increase and improves performance)
– Increase of the clock speed
• Increase productivity:
– Increase equipment throughput
– Increase manufacturing yields
– Increase the number of chips on a wafer:
• reduce the area of the chip: smaller feature size & redesign
– Use the largest wafer size available

Paulo Moreira CMOS technology 7

 “CMOS building blocks”
• “Making Logic”
• Silicon switches:
– The NMOS
– Its mirror image, the PMOS
• Electrical behavior:
– Strong inversion
• Model
• How good is the approximation?
– Weak inversion
– Gain and inversion

Paulo Moreira CMOS technology 8

 “Making Logic”
• Logic circuit “ingredients”:
– Power source
– Switches
– Power gain
– Inversion
• Power always comes from
some form of external EMF
generator.
• NMOS and PMOS
transistors:
– Can perform the last three
functions
– They are the building blocks
of CMOS technologies!

Paulo Moreira CMOS technology 9

 Silicon switches: the NMOS

Paulo Moreira CMOS technology 10

 Silicon switches: the NMOS
Abovesilicon:
Above silicon:
Thinoxide
••Thin oxide(SiO
(SiO)2)under
underthe
thegate
gateareas;
areas;
2
••Thick
Thickoxide
oxideeverywhere
everywhereelse;
else;

Paulo Moreira CMOS technology 11

 Silicon switches: the PMOS

Paulo Moreira CMOS technology 12

 MOSFET equations
• Cut-off region
I ds  0 for Vgs  VT  0

• Linear region
 V 
2
W
 
I ds   Cox   Vgs  VT Vds  ds  1   Vds  for 0  Vds  Vgs  VT
L  2 
 
• Saturation
 Cox W
I ds 
2

  Vgs  VT
L
 2
1   Vds  for Vds  Vgs  VT

• Oxide capacitance

Cox  ox
t ox
F / m2  0.24mprocess
0.24m process

• Process “transconductance” ttoxox==5nm

5nm(~10
(~10atomic
atomic
layers)
layers)
 Cox 
 ox
t ox
A/V
2
 CCoxox==5.6fF/m
5.6fF/m22

Paulo Moreira CMOS technology 13

 MOS output characteristics
• Cut off: Vgs < Vt
• Linear region: Vds<Vgs-VT
– Voltage controlled resistor
• Saturation region: Vds>Vgs-VT
– Voltage controlled current
source
– Deviation from the ideal
current source caused by
channel modulation

Ids
D

G
Vds
Vgs
S S

Paulo Moreira CMOS technology 14

 MOS output characteristics
L = 240nm, W = 480nm
250
Vgs = 0.7V (< Vt)
Vgs = 1.3V
Vgs = 1.9V
200 Vgs = 2.5V

150
Ids [uA]

100

50

0
0 0.5 1 1.5 2 2.5
Vds [V]

Paulo Moreira CMOS technology 15

 MOS output characteristics
L = 24um, W = 48um
400
Vgs = 0.7V (<Vt)
350 Vgs = 1.3V
Vgs = 1.9V
Vgs = 2.5V
300

250
Ids [uA]

200

150

100

50

0
0 0.5 1 1.5 2 2.5
Vds [V]

Paulo Moreira CMOS technology 16

 Bulk effect
• The threshold depends on: V=0 V=VT0
– Gate oxide thickness
– Doping levels
– Source-to-bulk voltage
• When the semiconductor
surface inverts to n-type p+ n+ n+
the channel is in “strong
inversion”
• Vsb = 0  strong inversion V>0 V>VT0

for:
– surface potential > -2F
• Vsb > 0  strong inversion
for: p+ n+ n+
– surface potential > -2F + Vsb

Paulo Moreira CMOS technology 17

 Bulk effect
600
W = 24m
L =L 48m
= 24um, W = 48um, Vbs = 1
500 L = 24um, W = 48um, Vbs = -1V
Vsb = 0V
Vsb = 1 V
400
Ids [uA]

300

200

100

0
0 0.5 1 1.5 2 2.5
Vgs [V]

Paulo Moreira CMOS technology 18

 Mobility

 C
 Cox 
ox 
ox
ox
t ox
t ox
AA//VV22

Thecurrent
The currentdriving
drivingcapability
capability
canbe
can beimproved
improvedbybyusing
usingmaterials
materials
withhigher
with higherelectron
electronmobility
mobility

Paulo Moreira CMOS technology 19

 Is the quadratic law valid?
Ids - Vgs (Vds = 2.5V, Vbs = 0V)
600
L = 24um, W = 48um
Quadratic“law”
Quadratic “law”valid
validfor
for
500 L = 2.4um, W = 4.8um longchannel
long channeldevices
devicesonly!
only!
L = 240nm, W = 480nm

400
Ids [uA]

300

200

100

0
0 0.5 1 1.5 2 2.5
Vgs [V]

Paulo Moreira CMOS technology 20

 Weak inversion
• Is Id=0 when Vgs<VT?
• For Vgs<VT the drain current
depends exponentially on Vgs
• In weak inversion and
saturation (Vds > ~150mV):
qVgs
W
I d  I do e nk T
L
where qVT

I do e nk T

• Used in very low power

designs
• Slow operation

Paulo Moreira CMOS technology 21

 Gain & Inversion
• Gain:
– Signal regeneration at
every logic operation
– “Static” flip-flops
– “Static” RW memory cells
• Inversion:
– Intrinsic to the common-
source configuration
• The gain cell load can
be:
– Resistor
– Current source
– Another gain device
(PMOS)

Paulo Moreira CMOS technology 22

 Simple MOS model for digital designers
• The MOS transistor “is” a capacitor whose voltage controls the
passage of current between two nodes called the source and
the drain.
• One of the electrodes of this capacitor is called the gate, the
other the source.
• The “way” the current flows between the source and the drain
depends on the gate-to-source voltage (Vgs) and on the drain-to-
source voltage (Vds).

Ids
D G D

G
Vds Vgs Cgs Ids Vds
Vgs
S S S S

Paulo Moreira CMOS technology 23

 Simple model
• If the gate-to-source voltage (Vgs) is less than a certain voltage,
called the threshold voltage (Vth), no current flows in the drain
circuit no matter what the drain-to-source voltage (Vds) is!
• This is the actual definition of threshold voltage Vth.
• That is, Ids = 0 for Vgs < Vth
• This is the same as saying that the drain circuit is an infinite
impedance (an open circuit)!
Ids
D G D

G
Vds Vgs Cgs Z= Vds
Vgs
S S S S

Paulo Moreira CMOS technology 24

 Simple model
• If the gate-to-source voltage (Vgs) is bigger than the threshold
voltage (Vth) and the drain-to-source voltage (Vds) is bigger than
Vgs – Vth then the drain current only depends on the gate
overdrive voltage (Vgs – Vth)
• That is, the drain circuit behaves as an “ideal” voltage controlled
current source:
 C W
I ds  ox  V  V 2
2 L gs T
Ids Ids
D G D

G
Vds Vgs Cgs I Vds
Vgs
S S S S

Paulo Moreira CMOS technology 25

 Simple model
• If the gate-to-source voltage (Vgs) is bigger than the threshold
voltage (Vth) and the drain-to-source voltage (Vds) is smaller
than Vgs – Vth then the drain current depends both on the gate
overdrive voltage (Vgs – Vth) and the drain-to-source voltage
(Vds)
• That is, the drain circuit behaves as a voltage controlled
resistor:
W

I ds  Cox  Vgs  VT Vds
L

Ids Ids
D G D

G
Vds Vgs Cgs R Vds
Vgs
S S S S

Paulo Moreira CMOS technology 26

 Simple model
• For PMOS transistors the same concepts are valid
except that:
– All voltages are negative (including Vth)
– Were we used bigger than you should use smaller than
– The drain current actually flows out of the transistor instead
of into the transistor.
• REMEMBER!
– This is a very simplistic model of the device!
– For detailed analog simulations one relies on complicated
SPICE models with many parameters defined by the
technology and transistor size
• However, it will allow us to understand qualitatively
the behaviour of CMOS logic circuits!
– Even some conclusions will be based on such a simple
model.
Paulo Moreira CMOS technology 27
 We digital designers care about delays
• In MOS circuits capacitive Ideal MOS
loading is the main cause.
VIN I (VGS-VT)2 C
(RC delay in the VGS
interconnects will be
addressed latter)
• Capacitance loading is due VIN
to: Vdd
– Device capacitance
– Interconnect capacitance
0
t

VV CC LL VOUT
delay
tt
CC    50% level
II CCox 
VVdd WW
Vdd
ox dd

Assuming
AssumingVVTT==00
0
t

Paulo Moreira CMOS technology 28

 MOSFET capacitances
• MOS capacitances have three origins:
– The basic MOS structure
– The channel charge
– The pn-junctions depletion regions

Ldrawn Gate
Source Drain
CGS Leff CGB CGD

CSB CDB
Bulk

Paulo Moreira CMOS technology 29

 MOS structure capacitances
• Source/drain diffusion Gate

extend below the gate

oxide by: W Source Drain
Source
xd - the lateral diffusion
xd xd
• This gives origin to the Gate-bulk
source/drain overlap overlap
L
capacitances:
tox
Cgso Cgdo Co W
Leff
Co (F / m) Cgso Cgdo
G/S overlap G/D overlap
• Gate-bulk overlap
Weff
capacitance:
Cgbo C o'  L, C o' (F / m) Source/Drain
Cgbo/2
Overlap Overlap

Paulo Moreira CMOS technology 30

 MOS structure capacitances
0.24m
0.24 process
mprocess
Notethat:
Note that:For
Forsmall
smallLLdevices
devicesthe
the
NMOS
NMOS overlapcapacitances
overlap capacitancesare arebecoming
becoming
L(drawn)=
L(drawn) =0.24
0.24m
m asimportant
importantas
asthe
the“intrinsic”
“intrinsic”gate
gate
as
L(effective)=
L(effective) =0.18
0.18m
m capacitance(C
(Cg==WWeffLLeffCCox))
W(drawn)= =22mm
capacitance g eff eff ox
W(drawn)
CCoo(s,
(s,d,
d,b)
b)==0.36
0.36fF/m
fF/m
CCoxox==5.6
5.6fF/m
fF/m22

CCgso =CCgdo=
gso=
gdo
=0.72
0.72fF
fF
CCgbo =0.086
gbo= 0.086fF
fF

CCgg=
=2.02
2.02fF
fF

Paulo Moreira CMOS technology 31

 Channel capacitance
• The channel capacitance is Cg = Weff Leff Cox
Gate-to-bulk
nonlinear Cg + Cgbo
Gate-to-source
• Its value depends on the
operation region 2/3 Cg + Cgso

1/2 Cg + Cgbo
• Its formed of three components:
Cgb - gate-to-bulk capacitance
Gate-to-drain
Cgs - gate-to-source capacitance Cgdo , Cgso

Cgd - gate-to-drain capacitance Cgbo

Off Saturated Linear

Operation region Cgb Cgs Cgd

Cutoff Cox W Leff 0 0
Linear 0 (1/2) Cox W Leff (1/2) Cox W Leff
Saturation 0 (2/3) Cox W Leff 0

Paulo Moreira CMOS technology 32

 Junction capacitances
0.24m process
mprocess
• Csb and Cdb are diffusion 0.24

capacitances composed of: NMOS

NMOS
L(drawn)=
L(drawn) =0.24
0.24mm
– Bottom-plate capacitance:
L(effective)=
L(effective) =0.18
0.18mm
Cbottom C j W Ls W(drawn)=
W(drawn) =22m
m
LLss= =0.8
0.8m
m
– Side-wall capacitance: CCj j(s,
(s,d)
d)==1.05
1.05fF/m
fF/m22
Csw C jsw 2 Ls  W  CCjsw
jsw==0.09
0.09fF/m
fF/m

CCbottom
bottom==1.68
1.68fF
fF
Side wall Bottom plate
CCsw
sw= =0.32
0.32fF
fF
Channel-stop
implant CCgg=
=2.02
2.02fF
fF
W
Notethat:
Note that:For
Forsmall
smallLLdevices
devicesthe
the
junctioncapacitances
junction capacitancesare arebecoming
becoming
asimportant
as importantasasthe
the“intrinsic”
“intrinsic”gate
gate
capacitance(C
capacitance (Cg==WWeffL LeffC
Cox))
g eff eff ox
Xj Channel
Ls

Paulo Moreira CMOS technology 33

 “Building a full MOS model
• MOS process parasitics
• pn-Junction diodes
• Depletion capacitance
• Source/drain resistance
• MOS Model
• Parasitic bipolars

Paulo Moreira CMOS technology 34

 MOS Parasitics
In a CMOS process the devices are:
• PMOS FETs
• NMOS FETs
+ unwanted (but ubiquitous):
• pn-Junction diodes
• parasitic capacitance
• parasitic resistance
and
• parasitic bipolars
• parasitic inductance

Paulo Moreira CMOS technology 35

 Parasitics or useful?
• Resistors
• Capacitors
• Inductors
• Diodes
• Bipolar transistors

Are useful circuit elements for analogue

circuit design. Some technologies offer the
possibility of manufacture such devices under
controlled conditions.

Paulo Moreira CMOS technology 36

 pn-Junction diodes
• pn – Junction diodes:
– Provide isolation between devices (if reversed
biased)
– Can be used to implement:
• band-gap circuits (if forward biased)
• variable capacitors
• clamping devices
• level shifting
– Are extremely useful as Electro Static Discharge
(ESD) protection devices.

Paulo Moreira CMOS technology 37

 CMOS devices
• Remember:
– Every source and drain creates a pn-junction
– pn-junctions must be reversed biased to provide isolation
between devices
– Reversed biased pn-junctions display parasitic capacitance

NMOS PMOS
Aluminium
contact
(Oxide cut)
Polysilicon
Gate Al Gate SiO2

W
L

p+ n+ n+ p+ p+ n+

p-substrate n-well

Substrate Source Drain Drain Source n-well

contact contact

Paulo Moreira CMOS technology 38

 pn-Junctions diodes
• Any pn-junction in the
IC forms a diode Al SiO2
Anode Cathode
• Majority carriers diffuse
from regions of high to
regions of low n+

concentration p-substrate
• The electric field of the Depletion region
depletion region Anode Diffusion Drift
e
counteracts diffusion n+ +
h
+ + + +
• In equilibrium there is 
- -
- -
no net flow of carriers in -
e
Cathode p
the diode h

Paulo Moreira CMOS technology 39

 Source/drain resistance
• Scaled down devices  higher source/drain
resistance: Ls,d
Rs,d  Rsq  Rc
W
• In sub- processes silicidation is used to reduce the
source, drain and gate parasitic resistance

Drain Source 0.24m

0.24 process
mprocess
contact contact
RR(P+)
(P+)==44/sq
/sq
RR(N-)
(N-)=
=44/sq
/sq

Ld Ls

Paulo Moreira CMOS technology 40

 Basic MOSFET model
• For designing we rely on D

simulators (SPICE) with

RD
appropriate models and
CGD CBD
parameters given by
technology supplier. - VBD +
G iD B
Rds - VBS +

CGS CBS

CGB
RS

Paulo Moreira CMOS technology 41

 CMOS parasitic bipolar
• Every p-n-p or n-p-n regions form parasitic bipolar
transistors.
• In standard MOS circuits these devices must be turned off.
– If not a latchup (short circuit) can occur
• For some applications (like bandgap circuits) these devices
can be used. But, better know what you are doing…
• For digital designs we “forget” about this
substrate n-well
contact Drain Gate Source contact

p+ p+ p+ n+

n-well

Paulo Moreira CMOS technology 42

 How do we make digital from this ?
• Logic levels
• MOST – a simple switch
• The CMOS inverter:
– DC operation
– Dynamic operation
– Propagation delay
– Power consumption
– Layout

Paulo Moreira CMOS technology 43

 CMOS logic: “0” and “1”
• Logic circuits process
Boolean variables Output Input

• Logic values are +V +V

"1"
associated with voltage
VOH
levels: Noise Margin
– VIN > VIH  “1” High
VIH
– VIN < VIL  “0” Undefined
region
• Noise margin: VIL
– NMH=VOH-VIH Noise Margin
Low
– NML=VIL-VOL VOL
"0"
0 0

Paulo Moreira CMOS technology 44

 The MOST - a simple switch
p-switch
S B
A B Y

p-switch
G A 0 0 bad 0 (source follower)
0 1 good 1
1 0 ? (high Z)
1 1 ? (high Z)
D Y

n-switch
D Y
A B Y
n-switch

G A 0 0 ? (high Z)
0 1 ? (high Z)
1 0 good 0
1 1 bad 1 (source follower)
S B

Paulo Moreira CMOS technology 45

 The CMOS inverter

VDD VDD

p-switch
A Y

A Y A Y 0 good 1

n-switch
1 good 0

VSS VSS

Paulo Moreira CMOS technology 46

 The CMOS inverter

VDD Inverter DC transfer characteristic

2.5
Slope = -1

2.5/0.25 2

1.5
A Y Vout (V) Vout=Vin
1

/0.25
0.5 Slope = -1

0
0 0.5 1 1.5 2 2.5
VSS Vin (V)

Paulo Moreira CMOS technology 47

 The CMOS inverter
Regions of operation (balanced inverter):

Vin n-MOS p-MOS Vout

0 cut-off linear Vdd
VTN<Vin<Vdd/2 saturation linear ~Vdd
Vdd/2 saturation saturation Vdd/2
Vdd-|VTP|>Vin>Vdd/2 linear saturation ~0
Vdd linear cut-off 0

Paulo Moreira CMOS technology 48

 The CMOS inverter
Inverter transient response
3
2.5
Vout
V out , V in (V)

2
1.5
1
0.5 CL=250fF
Vin
0
-0.5
0 2 4 6 8 10 12
Time (ns)

0.6
CL=250fF
0.4 I D(nmos)
I D (mA)

0.2
0
-0.2
-0.4
I D(pmos)
-0.6
0 2 4 6 8 10 12
Time (ns)

Paulo Moreira CMOS technology 49

 The CMOS inverter
• Propagation delay
– Main origin: load capacitance
C L Vdd CL
t pLH  2

k p Vdd  VTP  k p Vdd
C L Vdd CL
t pHL  2

k n Vdd  VTN  k n Vdd

1 CL  1 1

t p  t pLH  t pLH 
2

2 Vdd
  
 kn k p 
– To reduce the delay:
• Reduce CL
• Increase kn and kp. That is, increase W/L

Paulo Moreira CMOS technology 50

 The CMOS inverter
• CMOS power budget:
– Dynamic power consumption:
• Charging and discharging of capacitors
– Short circuit currents:
• Short circuit path between power rails during
switching
– Leakage
• Leaking diodes.
• Leaking transistors:
– Sub-threshold currents
– In the future devices gate leakage current!?

Paulo Moreira CMOS technology 51

 The CMOS inverter
• The dynamic power dissipation is a function of:
– Frequency
– Capacitive loading CMOS
CMOSlogic:
logic:
– Voltage swing no
nostatic
staticpower
power
consumption!
consumption!
• To reduce dynamic power dissipation
– Reduce: CL
– Reduce: f
– Reduce: Vdd  The most effective action

Dynamic power VDD

1 2
E = Energy / transition = C L Vdd
Vin Vout
2
2
P = Power = 2 f E  f C L Vdd

Paulo Moreira CMOS technology 52

 The CMOS inverter

substrate
contact (p+) n-well
n-well
polysilicon contact (n+)

n+ diffusion p+ diffusion
metal

Paulo Moreira CMOS technology 53

 The CMOS inverter

substrate contact (p+)

n-well contact (n+)
n-well polysilicon
diffusion contacts

n+ diffusions
p+ diffusions

polysilicon contacts

Paulo Moreira CMOS technology 54

• Scale between N and P MOS
• How to make a buffer

Paulo Moreira CMOS technology 55

 CMOS technology
• An Integrated Circuit is an
electronic network fabricated in
a single piece of a
semiconductor material
• The semiconductor surface is
subjected to various processing
steps in which impurities and
other materials are added with
specific geometrical patterns
• The fabrication steps are
sequenced to form three
dimensional regions that act as
transistors and interconnects
that form the switching or
amplification network

Paulo Moreira CMOS technology 56

 Lithography
Lithography: process used to transfer patterns to each
layer of the IC
Lithography sequence steps:
• Designer:
– Drawing the “layer” patterns on a layout editor
• Silicon Foundry:
– Masks generation from the layer patterns in the design data
base
• Masks are not necessarily identical to the layer patterns but
they are obtained from them.
– Printing: transfer the mask pattern to the wafer surface
– Process the wafer to physically pattern each layer of the IC

Paulo Moreira CMOS technology 57

 Lithography
Basic sequence 1. Photoresist coating
Photoresist
• The surface to be patterned is:
– spin-coated with photoresist SiO2

– the photoresist is dehydrated in an Substrate

oven (photo resist: light-sensitive 2. Exposure

Opaque
organic polymer) Ultra violet light

• The photoresist is exposed to ultra

Mask
violet light:
– For a positive photoresist exposed Unexposed Exposed

areas become soluble and non

exposed areas remain hard
• The soluble photoresist is chemically Substrate
removed (development). 3. Development
– The patterned photoresist will now
serve as an etching mask for the SiO2

Substrate

Paulo Moreira CMOS technology 58

 Lithography
• The SiO2 is etched away leaving 4. Etching

the substrate exposed:

– the patterned resist is used as
the etching mask
• Ion Implantation: Substrate

– the substrate is subjected to 5. Ion implant

highly energized donor or
acceptor atoms
– The atoms impinge on the
surface and travel below it
– The patterned silicon SiO2 serves Substrate
as an implantation mask
• The doping is further driven into 6. After doping

the bulk by a thermal cycle

diffusion Substrate

Paulo Moreira CMOS technology 59

 Lithography
• The lithographic sequence is repeated for
each physical layer used to construct the IC.
The sequence is always the same:
– Photoresist application
– Printing (exposure)
– Development
– Etching

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 Lithography
Patterning a layer above the silicon surface
1. Polysilicon deposition 4. Photoresist development
Polysilicon

SiO2
Substrate Substrate
2. Photoresist coating 5. Polysilicon etching
photoresist

Substrate Substrate
3. Exposure UV light
6. Final polysilicon pattern

Substrate Substrate

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 Lithography
• Etching: anisotropic etch (ideal)
resist
– Process of removing
unprotected material
layer 1
– Etching occurs in all directions
– Horizontal etching causes an layer 2
under cut
– “preferential” etching can be
isotropic etch
used to minimize the undercut
undercut resist
• Etching techniques:
– Wet etching: uses chemicals to layer 1
remove the unprotected
layer 2
materials
– Dry or plasma etching: uses
ionized gases rendered
preferential etch
chemically active by an rf-
undercut resist
generated plasma
layer 1
layer 2

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 Physical structure
Physical structure Layout representation Schematic representation

CVD oxide
Poly gate Metal 1

Source Ldrawn Drain Ldrawn G

S D
n+ n+ Wdrawn
Leffective
B
Gate oxide

p-substrate (bulk)

NMOS physical structure: NMOS layout representation:

– p-substrate • Implicit layers:
– n+ source/drain – oxide layers
– gate oxide (SiO2) – substrate (bulk)
– polysilicon gate • Drawn layers:
– CVD oxide – n+ regions
– metal 1 – polysilicon gate
– Leff<Ldrawn (lateral doping effects) – oxide contact cuts
– metal layers

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 Physical structure
Physical structure Layout representation Schematic representation

CVD oxide
Poly gate Metal 1

Source Ldrawn Drain

Ldrawn G

S D
p+ p+ Wdrawn
Leffective
B
Gate oxide
n-well (bulk) n-well

p-substrate

PMOS physical structure: PMOS layout representation:

– p-substrate • Implicit layers:
– n-well (bulk) – oxide layers
– p+ source/drain • Drawn layers:
– gate oxide (SiO2) – n-well (bulk)
– polysilicon gate – n+ regions
– CVD oxide – polysilicon gate
– metal 1 – oxide contact cuts
– metal layers

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 CMOS fabrication sequence
0. Start:
– For an n-well process the starting point is a p-type silicon wafer:
– wafer: typically 75 to 300mm in diameter and less than 1mm thick
1. Epitaxial growth:
– A single p-type single crystal film is grown on the surface of the
wafer by:
• subjecting the wafer to high temperature and a source of dopant
material
– The epi layer is used as the base layer to build the devices
– Advanced technologies use high resistively substrates (non-epi)

p-epitaxial layer Diameter = 75 to 230mm

300 mm

< 1mm
P+ -type wafer

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 CMOS fabrication sequence
2. N-well Formation:
– PMOS transistors are fabricated in n-well regions
– The first mask defines the n-well regions
– N-well’s are formed by ion implantation or deposition and diffusion
– Lateral diffusion limits the proximity between structures
– Ion implantation results in shallower wells compatible with today’s
fine-line processes

Physical structure cross section Mask (top view)

n-well mask
Lateral
diffusion

n-well

p-type epitaxial layer

Paulo Moreira CMOS technology 66

 CMOS fabrication sequence
3. Active area definition:
– Active area:
• planar section of the surface where transistors are build
• defines the gate region (thin oxide)
• defines the n+ or p+ regions
– A thin layer of SiO2 is grown over the active region and covered
with silicon nitride

Stress-relief oxide Silicon Nitride Active mask

n-well

p-type

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 CMOS fabrication sequence
4. Isolation:
– Parasitic (unwanted) FET’s exist between unrelated transistors
(Field Oxide FET’s)
– Source and drains are existing source and drains of wanted devices
– Gates are metal and polysilicon interconnects
– The threshold voltage of FOX FET’s are higher than for normal
FET’s

Parasitic FOX device

n+ n+ n+ n+

p-substrate (bulk)

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 CMOS fabrication sequence
– FOX FET’s threshold is made high by:
• introducing a channel-stop diffusion that raises the impurity
concentration in the substrate in areas where transistors are not
required
• making the FOX thick
4.1 Channel-stop implant
– The silicon nitride (over n-active) and the photoresist (over n-well)
act as masks for the channel-stop implant

Implant (Boron) channel stop mask = ~(n-well mask)

resit

n-well

p+ channel-stop implant
p-type

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 CMOS fabrication sequence
4.2 Local oxidation of silicon (LOCOS)
– The photoresist mask is removed
– The SiO2/SiN layers will now act as a masks
– The thick field oxide is then grown by:
• exposing the surface of the wafer to a flow of oxygen-rich gas
– The oxide grows in both the vertical and lateral directions
– This results in a active area smaller than patterned

patterned active area

Field oxide (FOX)

n-well
active area after LOCOS

p-type

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 CMOS fabrication sequence
• Silicon oxidation is obtained by:
– Heating the wafer in a oxidizing atmosphere:
• Wet oxidation: water vapor, T = 900 to 1000ºC (rapid process)
• Dry oxidation: Pure oxygen, T = 1200ºC (high temperature required to
achieve an acceptable growth rate)
• Oxidation consumes silicon
– SiO2 has approximately twice the volume of silicon
– The FOX recedes below the silicon surface by 0.46XFOX

Field oxide

XFOX
0.54 XFOX Silicon surface
0.46 XFOX

Silicon wafer

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 CMOS fabrication sequence
5. Gate oxide growth
– The nitride and stress-relief oxide are removed
– The devices threshold voltage is adjusted by:
• adding charge at the silicon/oxide interface
– The well controlled gate oxide is grown with thickness tox

n-well

p-type

Gate oxide
tox tox

n-well

p-type

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 CMOS fabrication sequence
6. Polysilicon deposition and patterning
– A layer of polysilicon is deposited over the entire wafer surface
– The polysilicon is then patterned by a lithography sequence
– All the MOSFET gates are defined in a single step
– The polysilicon gate can be doped (n+) while is being deposited to
lower its parasitic resistance (important in high speed fine line
processes)

Polysilicon mask
Polysilicon gate

n-well

p-type

Paulo Moreira CMOS technology 73

 CMOS fabrication sequence
7. PMOS formation
– Photoresist is patterned to cover all but the p+ regions
– A boron ion beam creates the p+ source and drain regions
– The polysilicon serves as a mask to the underlying channel
• This is called a self-aligned process
• It allows precise placement of the source and drain regions
– During this process the gate gets doped with p-type impurities
• Since the gate had been doped n-type during deposition, the final type
(n or p) will depend on which dopant is dominant
p+ implant (boron)
p+ mask

n-well
Photoresist
p-type

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 CMOS fabrication sequence
8. NMOS formation
– Photoresist is patterned to define the n+ regions
– Donors (arsenic or phosphorous) are ion-implanted to dope the n+
source and drain regions
– The process is self-aligned
– The gate is n-type doped

n+ implant (arsenic or phosphorous)

n+ mask

n-well
Photoresist
p-type

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 CMOS fabrication sequence
9. Annealing
– After the implants are completed a thermal annealing cycle is
executed
– This allows the impurities to diffuse further into the bulk
– After thermal annealing, it is important to keep the remaining
process steps at as low temperature as possible

n-well
n+ p+
p-type

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 CMOS fabrication sequence
10. Contact cuts
– The surface of the IC is covered by a layer of CVD oxide
• The oxide is deposited at low temperature (LTO) to avoid that
underlying doped regions will undergo diffusive spreading
– Contact cuts are defined by etching SiO2 down to the surface to be
contacted
– These allow metal to contact diffusion and/or polysilicon regions

Contact mask

n-well
n+ p+
p-type

Paulo Moreira CMOS technology 77

 CMOS fabrication sequence
11. Metal 1
– A first level of metallization is applied to the wafer surface and
selectively etched to produce the interconnects

metal 1 mask
metal 1

n-well
n+ p+
p-type

Paulo Moreira CMOS technology 78

 CMOS fabrication sequence
12. Metal 2
– Another layer of LTO CVD oxide is added
– Via openings are created
– Metal 2 is deposited and patterned

metal 2
Via metal 1

n-well
n+ p+
p-type

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 CMOS fabrication sequence
13. Over glass and pad openings
– A protective layer is added over the surface:
– The protective layer consists of:
• A layer of SiO2
• Followed by a layer of silicon nitride
– The SiN layer acts as a diffusion barrier against contaminants
(passivation)
– Finally, contact cuts are etched, over metal 2, on the passivation to
allow for wire bonding.

Paulo Moreira CMOS technology 80

 Advanced CMOS processes
• Shallow trench isolation
• n+ and p+-doped polysilicon gates (low threshold)
• source-drain extensions LDD (hot-electron effects)
• Self-aligned silicide (spacers)
• Non-uniform channel doping (short-channel effects)

n+ poly p+ poly
Silicide Oxide spacer

n+ p-doping
n+ p+ n-doping
p+
n-well
Shallow-trench isolation
Source-drain
p-type substrate extension

Paulo Moreira CMOS technology 81

 Process enhancements
• Up to six metal levels in modern processes
• Copper for interconnections
• Stacked contacts and vias
• Chemical Metal Polishing for technologies with
several metal levels
• For analogue applications some processes offer:
– capacitors
– resistors
– bipolar transistors (BiCMOS)

Paulo Moreira CMOS technology 82

 Yield
• Yield
number of good chips on wafer
Y
total number of chips
Yield tendency
100
• The yield is influenced by:
80
– the technology
60
– the chip area
– the layout 40
• Scribe cut and packaging

Yield (%)
also contribute to the final
yield
20
• Yield can be approximated 1.0 defects/cm2
by: Y e  AD 2.5 defects/cm2
5.0 defects/cm2
A - chip area (cm2) 10
0 2 4 6 8 10
D - defect density (defects/cm2)
Chip edge ( area in mm)

Paulo Moreira CMOS technology 83

 Design rules
• The limitations of the patterning process give rise to a
set of mask design guidelines called design rules
• Design rules are a set of guidelines that specify the
minimum dimensions and spacings allowed in a
layout drawing
• Violating a design rule might result in a non-functional
circuit or in a highly reduced yield
• The design rules can be expressed as:
– A list of minimum feature sizes and spacings for all the
masks required in a given process
– Based on single parameter  that characterize the linear
feature (e.g. the minimum grid dimension).  base rules
allow simple scaling

Paulo Moreira CMOS technology 84

 Design rules
• Minimum line-width: Minimum width
– smallest dimension
permitted for any object in
the layout drawing
(minimum feature size)
• Minimum spacing:
– smallest distance permitted
between the edges of two
objects
• This rules originate from the
resolution of the optical
printing system, the etching
process, or the surface
roughness

Minimum spacing

Paulo Moreira CMOS technology 85

 Design rules
• Contacts and vias: Contact
– minimum size limited by the metal 1
lithography process
– large contacts can result in
cracks and voids n+
p
– Dimensions of contact cuts
are restricted to values that Contact size
can be reliably d
manufactured metal 1
– A minimum distance d
between the edge of the
oxide cut and the edge of n+ diffusion
the patterned region must
Registration tolerance
be specified to allow for x2
misalignment tolerances metal 1
(registration errors)
x1
n+ diffusion

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 Design rules
• MOSFET rules
– n+ and p+ regions are
formed in two steps: Correct mask sizing
• the active area openings overlap active
allow the implants to x
penetrate into the silicon
substrate n+
• the nselect or pselect
provide photoresist p-substrate
x
openings over the active nselect
areas to be implanted
– Since the formation of the
diffusions depend on the Incorrect mask sizing
overlap of two masks, the overlap active
nselect and pselect regions x
must be larger than the
corresponding active areas n+
to allow for misalignments p-substrate
x nselect

Paulo Moreira CMOS technology 87

 Design rules
• Gate overhang: gate overhang
– The gate must overlap the
active area by a minimum
amount
– This is done to ensure that a
misaligned gate will still
yield a structure with no overhang
separated drain and source
regions
• A modern process have
thousands of rules to be
verified
no overhang
– Programs called Design
and misalignment
Rule Checkers assist the
designer in that task Short circuit

Paulo Moreira CMOS technology 88

 Technology scaling
• Scaling objectives
• Scaling variables
• Scaling consequences:
– Device area
– Transistor density
– Gate capacitance
– Drain current
– Gate delay
– Power
– Power density
– Interconnects

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 Scaling, why is it done?

Paulo Moreira CMOS technology 90

 Technology scaling
• Technology scaling has a threefold objective:
– Increase the transistor density
– Reduce the gate delay
– Reduce the power consumption
• At present, between two technology
generations, the objectives are:
– Doubling of the transistor density;
– Reduction of the gate delay by 30% (43% increase
in frequency);
– Reduction of the power by 50% (at 43% increase
in frequency);

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 Technology scaling
• How is scaling achieved?
– All the device dimensions (lateral and vertical) are
reduced by 1/
– Concentration densities are increased by 
– Device voltages reduced by 1/ (not in all scaling
methods)
– Typically 1/ = 0.7 (30% reduction in the
dimensions)

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 Technology scaling
• The scaling variables are:
– Supply voltage: Vdd  Vdd / 
– Gate length: L  L/
– Gate width: W  W/
– Gate-oxide thickness: tox  tox / 
– Junction depth: Xj  Xj / 
– Substrate doping: NA  NA  
This is called constant field scaling because the electric field
across the gate-oxide does not change when the technology is
scaled
If the power supply voltage is maintained constant the scaling is
called constant voltage. In this case, the electric field across
the gate-oxide increases as the technology is scaled down.
Due to gate-oxide breakdown, below 0.8µm only “constant
field” scaling is used.
Paulo Moreira CMOS technology 93
 Scaling consequences
Some consequences of 30% scaling in the
constant field regime ( = 1.43, 1/ = 0.7):

• Device/die area:
W  L  (1/)2 = 0.49
– In practice, microprocessor die size grows about 25% per
technology generation! This is a result of added functionality.

• Transistor density:
(unit area) /(W  L)  2 = 2.04
– In practice, memory density has been scaling as expected.
(not true for microprocessors…)

Paulo Moreira CMOS technology 94

 Scaling consequences
• Gate capacitance:
W  L / tox  1/ = 0.7

• Drain current:
(W/L)  (V2/tox)  1/ = 0.7

• Gate delay:
(C  V) / I  1/ = 0.7
Frequency   = 1.43
– In practice, microprocessor frequency has doubled every
technology generation (2 to 3 years)! This faster increase
rate is due to highly pipelined architectures (“less gates per
clock cycle”)

Paulo Moreira CMOS technology 95

 Scaling consequences
• Power:
C  V2  f  (1/)2 = 0.49

• Power density:
1/tox  V2  f  1

– In practice due to the faster increase in frequency power density

has also been increasing
• Active capacitance/unit-area:
Power dissipation is a function of the operation frequency, the power
supply voltage and of the circuit size (number of devices).
If we normalize the power density to V2  f we obtain the active
capacitance per unit area for a given circuit. This parameter can be
compared with the oxide capacitance per unit area:
1/tox   = 1.43
– In practice, for microprocessors, the active capacitance/unit-area
only increases between 30% and 35%. Thus, the twofold
improvement in logic density between technologies is not achieved:
new microprocessors integrate relatively more memory that the
previous generation.

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 Scaling consequences
• Interconnects scaling:
– Higher densities are only possible if the
interconnects also scale.
– Reduced width  increased resistance
– Denser interconnects  higher capacitance
– To account for increased parasitics and integration
complexity more interconnection layers are
added:
• thinner and tighter layers  local interconnections
• thicker and sparser layers  global interconnections and
power
Interconnects are scaling as expected

Paulo Moreira CMOS technology 97

 Scaling consequences
Parameter Constant Field Constant Voltage
Supply voltage (Vdd) 1/ 1
Length (L) 1/ 1/
Width (W) 1/ 1/ Scaling
Gate-oxide thickness (tox) 1/ 1/ Variables
Junction depth (Xj) 1/ 1/
Substrate doping (NA)  
Electric field across gate oxide (E)1 
Depletion layer thickness 1/ 1/
Gate area (Die area) 1/2 1/2 Device
Repercussion
Gate capacitance (load) (C) 1/ 1/
Drain-current (Idss) 1/ 
Transconductance (gm) 1 
Gate delay 1/ 1/2
Current density  3 Circuit
DC & Dynamic power dissipation 1/2  Repercussion
Power density 1 3
Power-Delay product 1/3 1/
Paulo Moreira CMOS technology 98