3.

4 PRODUCT
OF SUMS
SIMPLIFICATION
10 May, 2021 Digital Logic design
 37

PRODUCT OF SUMS SIMPLIFICATION

• The 1’s placed in the squares of the map represent
the
minterms of the function.
• The minterms not included in the function denote
the complement of the function.
• Mark the empty squares by 0’s
• Combine them into valid adjacent squares
• Obtain simplified expression of the complement function
F’.
 38

PRODUCT OF SUMS SIMPLIFICATION

• Simplify the following function in (a) sum of product and (b)
product of
sums:F (A, B,ABC, D) = ∑ (0,1, 2, 5, 8, 9, 10)
CD C
0 0 1 1 F = B’D’ + B’C’ +
0 1 1 0
0
m0 m1 m3 m2 A’C’D
0 1 1 0 1

0
m4 m5 m7 m6 F’ = AB+ CD + BD’
1 0 1 0 0
B Apply DeMorgan’s
m12 m13 m15 m14
1 theorem
1 0 0 0 0
A
m8 m9
1 m11 m10 (F’ = (AB + CD + BD’))’
0 1 1 0 1

F = (A’ + B’) (C’ + D’)

D (B’ + D)
 39

PRODUCT OF SUMS SIMPLIFICATION

B’ A
D’ ’
B
’
C’
F F
C D’
’

A’
D
D

F = B’D’ + B’C’ + F = (A’ + B’) (C’ + D’)

A’C’D (B’ + D)

Sum of Products Products of Sum

 40

PRODUCT OF SUMS SIMPLIFICATION

• Consider the function x y z F

defined in 0 0 0 0
Table 3.2. 0 0 1 1
• Sum of minterms:
F (x, y, z) = ∑ (1, 3, 4, 6)
0 1 0 0
–
0 1 1 1
• Product of maxterms:
F (x, y, z) = ∐ (0,2,5,7)
BC B 1 0 0 1
A
–
00 01 11 10
1 0 1 0
m0 m1 m3 m2
0 1 1 0 1
0 1 1 0
m4 m5 m7 m6
1 1 1 0
A
1 0 0 1
1

C
 41

PRODUCT OF SUMS SIMPLIFICATION

• y y
Sum of minterms:
x z 0 0 1 1
– F (x, y, z) = ∑ m0 0 m1 1 m3 1 m2 0
0
(1, 3, 4, 6) 0 1 1 0

• –
ProductSum of products:
of maxterms:
m4 m5 m7 m6
x’z + xz’ x
1 0 0 1
F (x, y, z) = ∐ (0,
1
–
2, 5, 7) z
– Product of sums:
(x’+z’) (x+z)
 3.5 DON’T CARE
CONDITIONS
10 May, 2021 Digital Logic design
 43

DON’ TCARE
•
CONDITIONS
The value of a function is not specified for certain
combinations of
variables
– BCD; 1010-1111: don't care

• These don’t care conditions can be used on a map to provide

further
simplification of the Boolean expression.
• Don’t care minterm is a combination of variables whole
logical value is not specified.
 44

DON’ TCARE
•
CONDITIONS
It cannot be marked with a 1 in the map
– It would require that the function always be a 1 for such
combination.

• It cannot be marked with a 0 in the map

– It would require that the function always be a 0 for such
combination.

• For don’t care conditions an X is used.

• For adjacent squares in the map to simplify the function
– The don’t care minterms may be assumed to be either 0 or
1.
 45

DON’ TCARE
CONDITIONS
• Simplify the Boolean function F (w, x, y, z) = ∑ (1, 3,
7, 11, 15)

∑0 (0,
yz y y y
–
wx Don’t
00 0care
1 conditions
11 10 d(w, x, y,wx
z) =
z 0 2, 5). 1 1
01 10
m0 m1 m3 m2
m0 m1 m3 m2 0
00 X 1 1 X
X 1 1 X 0
m4 m5 m7 m6
m4 m5 m7 m6
01 0 X 1 0
0 X 1 0 0 x
x 1 m12 m13 m15 m14
m12 m13 m15 m14
1
11 1 0 0 1 0
0 0 1 0
w w m8 m9
m11 m10
m8 m9
m11 m10
10 1 0 0 1 0
0 0 1 0 0
w’ F = yz +
F
yz= +x’ z
w’z
z
 46

DON’ TCARE
•
CONDITIONS
Don’t care minterms in the map are initially marked with X’s.
• The choice between 0 and 1 is made depending on the way the
incompletely specified function is simplified.
• Once the choice is made,
– the simplified function obtained will consist of a sum of minterms
– including those minterms that were initially marked with X’s and
– have been chosen to be included with 1’s.

• F(w, x, y, z) = yz + w’x’ = ∑ (0, 1, 2, 3, 7, 11, 15)

• F(w, x, y, z) = yz + w’z = ∑ (0, 1, 3, 5, 7, 11, 15)

 3.6 NAND AND NOR
IMPLEMENTATIONS
10 May, 2021 Digital Logic design
 48

NAND AND NOR IMPLEMENTATIONS

NAND Circuits:
Inverte x x
• The NAND gate is a r ’
universal gate.
– Can implement any
digital system. x
– Complement operation is AN x
D y y
obtained from one-input
NAND gate.
– AND operation requires two
NAND gates x
– OR operation is
achieved through O (x’y’)’ = x
NAND gate with R +y
additional inverters in y
each input
 49

NAND AND NOR IMPLEMENTATIONS

NAND Circuits:
• Two graphic symbols for NAND
gate

x x
(xyz (x’ + y’ + z’) =
y )’ y (xyz)’
z z

(a) AND- (b) Invert-

invert OR
 50

NAND AND NOR IMPLEMENTATIONS

• The implementation of Boolean functions with
NAND gates
– Require that the function be in sum of products form.
– F = A.B + C.D
A A A
B B B
F F F

C C C
D D D

(a (b (c
) ) )

(a) F = A.B +C.D (b) F = ((A.B)’)’ + (c) F = ((A.B)’

((C.D)’)’ (C.D)’)’
= (A+B)’ + (C+D)’ = ((A+B) (C +
D))’
= A.B + C.D = A.B + C.D
 51

NAND AND NOR IMPLEMENTATIONS

• Implement the following Boolean function F = (x ,y, z) = (1,
2, 3, 4, 5, 7).
– Simplify the yfunction in sum of products
y using K-map.
x z F=z+
0 0 1 1
xy’+ x’y
m0
0 m1
1 m1
3 m0
2
0
1 1 1
m4 m5 m7 m6
x
1 1 1 1

z
 52

NAND AND NOR IMPLEMENTATIONS

y y
x z 0 0 1 1 F=z+
m0
0 m1
1 m1
3 m0
2
xy’+ x’y
0
1 1 1
m4 m5 m7 m6
x
1 1 1 1

z
x x x
y y y
’ ’

x x x
’ F ’ F F
y
y y

z z z
’
(a (b (c
) ) )
 53

NAND AND NOR IMPLEMENTATIONS

• The procedure
– Simplify in the form of sum of products;

– Draw a NAND gate for each product term;

 The inputs to each NAND gate are the literals of the term (the
first level);

– A single NAND gate for the second sum term (the second
level);
– A term with a single literal requires an inverter in the first
level if the single literal is not complemented. Otherwise it
can be connected directly.
 54

NAND AND NOR IMPLEMENTATIONS

• General procedure for converting multilevel AND-OR
diagram into all
NAND diagram:
– Convert all AND gates to NAND gates with AND-invert graphic
symbol.
– Convert all OR gates to NAND gates with invert-OR graphic
symbol.
– Check all the bubbles in the diagram.
• For every bubble that is not compensated by another small circle
along the same line,
• insert an inverter (one-input NAND gate) or
 55

NAND AND NOR IMPLEMENTATIONS

• F = A (CD + B) +
BC’ C

(a) AND-OR
B gates

C
C
D
’

(b) NAND
B gates
 56

NAND AND NOR IMPLEMENTATIONS

• F = (AB’ + A’B) (C
+ D’) A

B
’

A
’
F
B
C

D
’
(a) AND-OR
gates
A

B
’

A
’
F
B
C
’

D
(b) NAND
gates
 57

NAND AND NOR IMPLEMENTATIONS

• NOR function is the
dual of Inverter
x’
x

NAND function.
x

• The NOR gate is

OR
y
x+
y

also universal.
x

AND (x’ + y’)’ =

x y
y
 58

NAND AND NOR IMPLEMENTATIONS

NAND Circuits:
• Two graphic symbols for NAND
gate

x x
(x+y+ (x’ y’ z’) = (x + y
y z)’ y + z)’
z z

(a) OR- (b) Invert-

invert AND
 59

NAND AND NOR IMPLEMENTATIONS

• Example: Implementing F = (A + B)
(C + D) E
A

B
’
F

E
’
• Example: Implementing F = (A B’ + A’ B)
(C + D’) A
’

B
F
A

B’

’
 Assignment 03 (EX: Problems) Due
Date: 07-07-2023
Question: 3.6
Question: 3.12

10 May, 2021 Digital Logic design