Direct Cache Mapping
Direct Cache Mapping
Cache size: 16 KB
Word size: 4 bytes (assuming a typical 32-bit architecture where each word is 4 bytes)
15
Direct Cache Mapping
0 0 1 2 3
3 12 13 14 15
Block Size : 4 Bytes
4 16 17 18 19
No. of Block in Main Memory: 64/4 = 16
5 20 21 22 23
6 24 25 26 27
0 0 7 28 29 30 31
0 1 8 32 33 34 35
1 0 9 36 37 38 39
1 1
10 40 41 42 43
11 44 45 46 47
48 49 50 51
12
52 53 54 55
13
56 57 58 59
14
60 61 62 63
15
Direct Cache Mapping
0 0 1 2 3
1 4 5 6 7
5 20 21 22 23
6 24 25 26 27
0 0 7 28 29 30 31
0 1 For 64 bytes
8 32 33 34 35
1 0 9 36 37 38 39
1 1
10 40 41 42 43
11 44 45 46 47
12 48 49 50 51
13 52 53 54 55
14 56 57 58 59
15 60 61 62 63
Direct Cache Mapping
0 1 2 3
0
4 5 6 7 1
8 9 10 11 2
P.A bits :
12 13 14 15 3 (Physical Address Bits)
16 17 18 19 4 0 0 -> 0th
20 21 22 23 5
0 1 -> 1st
1 0 -> 2nd
24 25 26 27 6
1 1 -> 3rd
28 29 30 31 7
16 Blocks
32 33 34 35 8
36 37 38 39 9
10
40 41 42 43
44 45 46 47 11
48 49 50 51 12
52 53 54 55 13
56 57 58 59 14
60 61 62 63 15
1 4 5 6 7
2 8 9 10 11
P.A bits : 3 12 13 14 15
5 20 21 22 23
0 1 1 1 1 1
6 24 25 26 27
7 28 29 30 31
3
8 32 33 34 35
7
9 36 37 38 39
10 40 41 42 43
11 44 45 46 47
= 31 12 48 49 50 51
13 52 53 54 55
14 56 57 58 59
15 60 61 62 63
Direct Cache Mapping
0 0 1 2 3
1 4 5 6 7
2 8 9 10 11
3 12 13 14 15
4 16 17 18 19
5 20 21 22 23
6 24 25 26 27 0 1 2 3 0
7 28 29 30 31
4 5 6 7 1
8 32 33 34 35
8 9 10 11 2
9 36 37 38 39
10
40 41 42 43
12 13 14 15
3
11 44 45 46 47
12 48 49 50 51
13 52 53 54 55
14 56 57 58 59
15 60 61 62 63
Direct Cache Mapping
Direct Cache Mapping
The bits in the Block offset
decides in which byte of the
identified block the required
content is present.
P.A bits :
(Physical Address Bits)
1 4 5 6 7
2 8 9 10 11 12 001100
3 12 13 14 15
13 001101
4 16 17 18 19
14 001110
15 001111
5 20 21 22 23
6 24 25 26 27 28 011100
7 28 29 30 31 29 011101
8 32 33 34 35
30 011110
9 36 37 38 39
31 011111
10
40 41 42 43 44 101100
11 44 45 46 47
45 101101
46 101110
12 48 49 50 51
47 101111
13 52 53 54 55
14 56 57 58 59 60 111100
15 60 61 62 63 61 111101
62 111110
63 111111
Direct Cache mapping
• In direct mapping physical address is divided into three parts i.e., Tag
bits, Cache Line Number and Byte offset.
Tag Number of Cache Lines Byte Offset
Bangladesh Bank Assistant Maintenance Engineer
Cache size: 16 KB
Word size: 4 bytes (assuming a typical 32-bit architecture where each word is 4 bytes)
Cache size: 16 KB
Word size: 4 bytes (assuming a typical 32-bit architecture where each word is 4 bytes)
Cache size: 16 KB
Word size: 4 bytes (assuming a typical 32-bit architecture where each word is 4 bytes)
Cache size: 16 KB
Word size: 4 bytes (assuming a typical 32-bit architecture where each word is 4 bytes)
Cache size: 16 KB
Word size: 4 bytes (assuming a typical 32-bit architecture where each word is 4 bytes)