Chapter 10

ONCHIP VARIATIONS
• The process and environmental parameters may not be uniform across different portions of
the die. Due to process variations, identical MOStransistors in different portions of the die
may not have similar characteristics. These differences are due to process variations within
the die.
1. local process variations
2. Global process variations

Besides the variations in the process parameters, different portions of the

design may also see different power supply voltage and temperature.
i. IR drop variation along the die area affecting the local power supply.
ii. Voltage threshold variation of the PMOS or the NMOS device.
iii. Channel length variation of the PMOS or the NMOS device.
iv. Temperature variations due to local hot spots.
• Modeling of OCV is not intended to model the entire span of the PVT variations
possible from wafer to wafer but to model the PVT variations that are possible
locally within a single die.
• The cell delays or wire delays or both can be derated to model the effect of OCV.
• The worst condition for setup check occurs when the launch clock path and the
data path have the OCV conditions which result in the largest delays, while the
capture clock path has the OCV conditions which result in the smallest delays.
LaunchClockPath + MaxDataPath <= ClockPeriod +
CaptureClockPath- Tsetup_UFF1
This implies that the minimum clock period = LaunchClockPath +
MaxDataPath- CaptureClockPath + Tsetup_UFF1
From the figure,
LaunchClockPath = 1.2 + 0.8 = 2.0
MaxDataPath = 5.2
CaptureClockPath = 1.2 + 0.86 = 2.06
Tsetup_UFF1 = 0.35
This results in a minimum clock period of:
2.0 + 5.2– 2.06 + 0.35 = 5.49ns
• Cell and net delays can be derated using the set_timing_derate
specification.
set_timing_derate-early 0.8
set_timing_derate-late 1.1
• The-cell_delay and the-net_delay options can be used in the set_timing_derate
specification
set_timing_derate-cell_delay-early 0.9
set_timing_derate-cell_delay-late 1.0
set_timing_derate-net_delay-early 1.0
set_timing_derate-net_delay-late 1.2
set_timing_derate-early 0.95-clock
set_timing_derate-late 1.05-data
• We now apply the following derating to the example ,
set_timing_derate-early 0.9
set_timing_derate-late 1.2
set_timing_derate-late 1.1-cell_check

• With these derating values, we get the following for setup check:
LaunchClockPath = 2.0 * 1.2 = 2.4
MaxDataPath = 5.2 * 1.2 = 6.24
CaptureClockPath = 2.06 * 0.9 = 1.854
Tsetup_UFF1 = 0.35 * 1.1 = 0.385

• This results in a minimum clock period of:

2.4 + 6.24– 1.854 + 0.385 = 7.171ns
• The pessimism caused by different derating factors applied on the common part
of the clock tree is called Common Path Pessimism (CPP) which should be
removed during the analysis. CPPR, which stands for Common Path Pessimism
Removal, is often listed as a separate item in a path report. It is also labeled as
Clock Reconvergence Pessimism Removal (CRPR).
CPP = LatestArrivalTime@CommonPoint-
EarliestArrivalTime@CommonPoint.
For the example of
LatestArrivalTime@CommonPoint = 1.2 * 1.2 = 1.44
EarliestArrivalTime@CommonPoint = 1.2 * 0.9 = 1.08
This implies a CPP of: 1.44- 1.08 = 0.36ns
With the CPP correction, this results in a minimum clock period of:
7.171- 0.36 = 6.811ns
• Analysis with OCV at Worst PVT Condition :
• If the setup timing check is being performed at the worst-case PVT condition, no
derating is necessary on the late paths as they are already the worst possible.
set_timing_derate-early 0.9
set_timing_derate-late 1.0
• OCV for Hold Checks :
• We now examine how the derating is done for a hold timing check.
• If the PVT conditions are different along the chip, the worst condition for hold
check occurs when the launch clock path and the data path have OCV conditions
which result in the smallest delays, that is, when we have the earliest
launchclock.
• The hold timing check is specified in the following expression for this example.
LaunchClockPath + MinDataPath- CaptureClockPath- Thold_UFF1 >= 0
• Applying the delay values in the Figure 10-2 to weget: LaunchClockPath =
the expression, we get 0.85 * 0.9 = 0.765
(without applying any derating): MinDataPath =
LaunchClockPath = 0.25 + 0.6 = 0.85 1.7 * 0.9 = 1.53.
MinDataPath = 1.7 CaptureClockPath =
1.00 * 1.2 = 1.2
CaptureClockPath = 0.25 + 0.75 = 1.00
Thold_UFF1 =
Thold_UFF1 = 1.25 1.25 * 0.95 = 1.1875
This implies that the condition is: Common clock path pessimism:
0.85 + 1.7– 1.00- 1.25 = 0.3n >=0 0.25 * (1.2- 0.9) = 0.075
which is true, and thus no hold violation exists. The hold check condition then
becomes:
Applying the following derate specification:
0.765 + 1.53– 1.2- 1.1875 +
set_timing_derate-early 0.9 0.075 =-0.0175ns
set_timing_derate-late 1.2 hold violation
set_timing_derate-early 0.95-cell_check
• Here is a holdtiming check path report for an example design that uses
this derating.
Time Borrowing
• The time barrowing technique, which is also called cycle
stealing, occurs at a latch.
• In a latch, one edge of the clock is called as opening edge,
where it opens the latch so that output of the latch is the same
as the data input, other edge of the clock is called as closing
edge, where any change on the data input is no longer
available at the output of the latch.
• Since a latch is transparent when the clock is active, the data
can arrive later than the active clock edge, that is, it can
borrow time from the next cycle.
• If such time is borrowed, the time available for the following
stage is reduced.
• The first rule in timing to a latch is that if the data arrives
before the opening edge of the latch, the behavior is modeled
exactly like a flip-flop. The opening edge captures the data and
the same clock edge launches the data as the start point for
the next path.
• The second rule applies when the data signal arrives while the
latch is transparent (between the opening and the closing
edge). The output of the latch, rather than the clock pin, is
used as the launch point for the next stage. The amount of
time borrowed by the path ending at the latch determines the
launch time for the next stage.
• A data signal that arrives after the closing edge at the latch is a
timing violation.
• Example of time borrowing using
the active rising edge.
• If data DIN is ready at time A prior
to the latch opening on the rising
edge of CLK at 10ns, the data flows
to the output of the latch as it
opens. If data arrives at time B as
shown for DIN (delayed), it
borrows time Tb.
• Figure 10-4 shows the timing
regions for data arrival for positive
slack, zero slack, and negative slack
(that is, when a violation occurs).
• Example of no time borrowing
• Example with time borrowed
• we analyze the timing from ULAT1 to DFF1 when time
borrowing occurs.
• Example with timing violation
Power Management
• Managing the power is an important aspect of any design and
how it is implemented.
• The power dissipated in the logic portion of the design is
comprised of leakage power and the active power.
• In general, there are two considerations for managing the
power contributions from the digital logic comprised of
standard cells and memory macros:

• To minimize the total active power of the design.

• To minimize the power dissipation of the design in standby mode.
• Clock Gating
• A flip-flop dissipates power due to clock toggle even when the
flip-flop output does not switch.
• The purpose of clock gating is to minimize this contribution by
eliminating the clock activity at the flip-flop during clock cycles
when the flip-flop input is not active.
• The logic restructuring through clock gating introduces gating of
the clock at the flip-flop pin.

• The clock gating thus ensures that the clock pin of the flip-flop
toggles only when new data is available at its data input.
• Power Gating
• Power gating involves gating off the power supply so that the
power to the inactive blocks can be turned off.
• This procedure is illustrated as a footer (or a header) MOS
device is added in series with the power supply.
• The control signal SLEEP is configured so that the footer (or a
header) MOS device is on during normal operation of the
block.
• During inactive (or sleep) mode of the block, the gating MOS
device is turned off which eliminates any active power
dissipation in the logic block.
• The footer and header devices introduce a series on resistance
to the power supply. If the value of the on resistance is not
small, the IR drop through the gating MOS device can affect
the timing of the cells in the logic block.
• Multi Vt Cells
• The multi Vt cells are used to tradeoff speed with leakage.
• high Vt cells < standard Vt cells < low Vt cells – leakage
• high Vt cells < standard Vt cells < low Vt cells – speed
• In most designs, the goal is to minimize the total power while
achieving the desired operational speed.
• Implementing a design with only high Vt cells to reduce
leakage can increase the total power even though the leakage
contribution may be reduced.
• High Performance Block with High Activity
• High Performance Block with Low Activity
• Well Bias
• The well bias refers to adding a small voltage bias to the P-well
or N-well used for the NMOS and PMOS devices respectively.
• The leakage power can be reduced significantly if the well
connections have a slight negative bias.
• This means that the P-well for the NMOS devices is connected
to a small negative voltage (such as -0.5V). Similarly, the N-well
connection for the PMOS devices is connected to a voltage
above the power rail (such as Vdd + 0.5V).
• By adding a well bias, the speed of the cell is impacted;
however the leakage is reduced substantially.
• The drawback of using well bias is that it requires additional
supply levels (such as -0.5V and Vdd+0.5V) for the P-well and
N-well connections.
 Data to Data checks
• Setup and hold checks can also be applied between any two arbitrary data pins, neither of
which is a clock.
• One pin is the constrained pin, which acts like a data pin of a flip-flop, and the second pin is the
related pin, which acts like a clock pin of a flip-flop.
• One important distinction with respect to the setup check of a flip-flop is that the data to data
setup check is performed on the same edge as the launch edge
• Thus, the data to data setup checks are also referred to as zero-cycle checks or same-cycle
checks.
• A data to data check is specified using the set_data_check constraint. Here are example SDC specifications.
set_data_check-from SDA-to SCTRL-setup 2.1
set_data_check-from SDA-to SCTRL-hold 1.5

• The setup data check implies that SCTRL should arrive at least 2.1ns prior to the edge of the related
pin SDA. Otherwise it is a data to data setup check violation.
• The hold data check specifies that SCTRL should arrive at least 1.5ns after SDA. If the constrained
signal arrives earlier than this specification, then it is a data to data hold check violation
• Consider the and cell shown in Figure . We assume the requirement is to ensure that PNA arrives 1.8ns before the
rising edge of PREAD and that it should not change for 1.0ns after the rising edge of PREAD.
• In this example, PNA is the constrained pin and PREAD is the related pin. The required waveforms are shown in
Figure
• Such a requirement can be specified using a data to data setup and hold check.
• set_data_check-from UAND0/A1-to UAND0/A2-setup 1.8
• set_data_check-from UAND0/A1-to UAND0/A2-hold 1.0
 • The zero-cycle setup check causes the • In some scenarios, a designer
hold timing check to be different from may require the data to data
other hold check reports- the hold check hold check to be performed on
is no longer on the same clock edge. the same clock cycle
• set_multicycle_path -1 -hold-to
UAND0/A2

The setup time is specified as data check

setup time in the report

This is the hold check report on

same clock edge for both pins
• An alternate way of having the data to data hold check performed in the same cycle is to
specify this as a data to data setup check between the pins in the reverse direction
set_data_check –from UAND0/A2 –to UAND0/A1 –setup 1.0

Non-Sequential Checks
• These checks are applied only to pins within a single cell or macro
• A non sequential check is a check between two pins, neither of which is a clock. One pin is the constrained
pin that acts like data, while the second pin is the related pin and this acts like a clock.
• The check specifies how long the data on the constrained pin must be stable before and after the change
on the related pin this check is specified as part of the cell library specification and no explicit data to data
check constraint is required.
Difference between the non sequential checks and data to data checks :

Data to Data checks

Non sequential checks

• Timing checks between two • Timing checks between two pins

data signals in a design of a cell, defined in the cell
• Defined by the designer library
based on the design needs • the setup and hold values are
and functionality. obtained from the standard cell
library
 Clock Gating Checks
• A clock gating check occurs when a gating
signal can control the path of a clock signal
at the logic cell.
• The pin of the logic cell connected to the
clock is called the clock pin and the pin
where the gating signal is connected to is
the gating pin.
• One condition for a clock gating check is
that the clock that goes through the cell
must be used as a clock downstream.
• Another condition for the clock gating
check applies to the gating signal. The
signal at the gating pin of the clock should
not be a clock or if it is clock, it should not
be used as a downstream.
Types of clock gating checks
• Active-high clock gating checks: Occurs when the gating cell has an and or nand function.
• Active-low clock gating checks: Occurs when the gating cell has an or or a nor function.
Active-high clock gating:
As it is an and cell, a high on gating signal UAND0/A opens up the gating cell and allows the clock to
propagate through.
The clock gating check is intended to validate that the gating pin transition does not create an active
edge for the fanout clock.
For positive edge-triggered logic, this implies that the raising signal occurs during the inactive period
of the clock.
Similarly, for negative edge-triggered logic, the falling edge of the gating signal should occur only
when the clock is low.
Active-Low Clock Gating:
• As it is an or cell, a low on gating
signal UOR1/A1 opens up the
gating cell and allows the clock to
propagate through.
• The transitions of gating signal
(rising or falling edges) must occur
only when clock is high. This is
because the gating signal should
not cause an active edge for the
output gated clock.
Clock Gating with a Multiplexer
• A clock gating check at the
multiplexer inputs ensures that
the multiplexer select signal
arrives at the right time to cleanly
switch between MCLK and TCLK.
• For this example, we are
interested in switching to and
from MCLK and assume that TCLK
is low when the select signal
switches.
Clock Gating with Clock Inversion

• Another clock gating example

where the clock to the flip-flop is
inverted and the output of the
flip-flop is the gating signal.
• Since the gating cell is an and
cell, the gating signal must switch
only when the clock signal at the
and cell is low.
The hold check validates whether the data (gating signal) changes before
the falling edge of MCLK at time 10ns.