Computer Organization

and Architecture
Carl Hamacher, Zvonko Vranesic, Safwat
Zaky,
Computer Organization, 5th
Edition,
Tata McGraw Hill, 2002.
 Module-1
Machine Instructions and
Programs
Numbers, Arithmetic
Operations, and
Characters
Introduction
 Computers are built using logic
circuits that operate on information
represented by two- valued
electrical signals
 Labelled as 0 and 1
 We define the amount of information
represented by such a signal as a bit of
information, where bit stands for binary
digit.
 The most natural way to represent a
Number Representation

𝐵 = 𝑏𝑛−1 … … 𝑏1𝑏0
 Consider an n-bit vector

Where 𝑏𝑖 = 0 𝑜𝑟 1 for 0 ≤ 𝑖
≤𝑛−1

integer values 𝑉 in the range 0 to 2𝑛

 This vector can represent unsigned

− 1, where
𝑉 𝐵 = 𝑏𝑛−1 × 2𝑛−1 + ⋯ + 𝑏1 × 21 + 𝑏0
× 20

Signed Integer
3 major representations:
 Sign-and-magnitude
 1’s complement
 2’s complement
 Assumptions:
 4-bit machine word
 16 different values can be
represented
 Roughly half are positive, half are
negative
Sign-and-Magnitude Representation

-7
-6 +0 +1
1111 0000
-5 1110 +2 +
1101 0010
0001
-4 1100 0 100 = + 4
0011 +3
-3 1011 0100 +4 1 100 = - 4
1010
-2 0101 -
1001 +5
-1 1000 0111 0110
+6
-0 +7
High order bit is sign: 0 = positive (or zero), 1 = negative
Three low order bits is the magnitude: 0 (000) thru 7 (111)
Number range for n bits = +/-2n-1 -1
Two representations for 0
1’s Complement Representation
-0
-1 +0 +1
1111 0000
-2 1110 +2 +
1101 0010
0001
-3 1100 0 100 = +
0011 +3
4
-4 1011 0100 +4 1 011 = -
4
1010
-5 0101 -
1001 +5
-6 1000 0111 0110
+6
-7 +7
 Subtraction implemented by addition & 1's
complement
 Still two representations of 0! This causes some

problems
 Some complexities in addition
2’s Complement Representation
-1
-2 +0 +1
1111 0000
-3 1110 +2 +
like 1's comp 1101 0010
0001
except shifted -4 1100 0 100 = +
one position 0011 +3
4
clockwise -5 1011 0100 +4 1 100 = -
4
1010
-6 0101 -
1001 +5
-7 1000 0111 0110
+6
-8 +7

 Only one representation for 0

 One more negative number than

positive
number
 Binary, Signed-Integer
Representations
B Values represented
Page
28 Sign and
b3 b 2 b 1 b 0 magnitude 1's complement 2's complement

0 1 1 1 +7 +7 + 7
0 1 1 0 +6 +6 + 6
0 1 0 1 +5 +5 + 5
0 1 0 0 +4 +4 + 4
0 0 1 1 +3 +3 + 3
0 0 1 0 +2 +2 + 2
0 0 0 1 +1 +1 + 1
0 0 0 0 +0 +0 + 0
1 0 0 0 - 0 -7 - 8
1 0 0 1 - 1 -6 - 7
1 0 1 0 - 2 -5 - 6
1 0 1 1 - 3 -4 - 5
1 1 0 0 - 4 -3 - 4
1 1 0 1 - 5 -2 - 3
1 1 1 0 - 6 - 1 - 2
1 1 1 1 - 7 -0 - 1

Figure 2.1. Binary, signed-integer representations.

Addition of Positive Numbers
Addition and Subtraction of
Signed Numbers
Addition and Subtraction – 2’s
Complement
 Toadd two numbers, add their n-bit
representations, ignoring the carry-out
signal from the most significant bit
(MSB) position. The sum will be the
algebraically correct value in the 2’s

the answer is in the range −2𝑛−1

complement representation as long as

through +2𝑛−1 − 1.
Addition and Subtraction – 2’s
Complement..
subtract two numbers 𝑋 and 𝑌,
that is, to perform 𝑋 − 𝑌, form the 2’s
 To

complement of 𝑌 and then add it to 𝑋.

Again, the result will be the
algebraically correct value in the 2’s

the answer is in the range −2𝑛−1

complement representation system if

+ 2𝑛−1 − 1.
through
Examples
4 -4 1100
0100
+ (-3) 1101
If carry-in to the high +3 0011
order bit = 7 0111 -7 11001
carry-out then ignore
carry
if carry-in differs from 4 0100 -4 1100
carry-out then overflow
-3 1101 +3 0011
1 10001 -1 1111

Simpler addition scheme makes twos complement the most common

choice for integer number systems within digital systems
 Examples 0010 ( + 2) 0100 ( + 4)
(a) ( + 3) (b)  - 6
+ 0011 + 1010
Page 0101 ( + 5) 1110  - 2
31 (c) 1011  - 5 (d) 0111 ( + 7)
+ 1110  - 2 + 1101  - 3
1001  - 7 0100 ( + 4)
(e) 1101  - 3 1101
- 1001  - 7 + 0111
0100 ( + 4)
(f) 0010 ( + 2) 0010
- 0100 ( + 4) + 1100
1110
 - 2
(g) 0110 ( + 6) 0110
- 0011 ( + 3) + 1101
0011
(h) 1001  - 7 ( + 3)
- 1011  - 5 1001
+ 1 01 11 00 1
 - 2
(i) 1001  - 7 1001
- 0001 ( + 1) + 1111
1000  - 8
(j) - 0
1 01 10 01 ( + 2) + 00001101
 - 3
0101
( + 5)
Figure 2.4. 2's-complement Add and Subtract operations.
Overflow - Add two positive numbers to get
a negative number or two negative numbers
to get a positive number

-1 +0 -1 +0
-2 1111 0000 +1 -2 1111 0000 +1
1110 0001 1110 0001
-3 +2 -3
1101 1101 +2
0010 0010
-4 -4
1100 0011 +3 1100 0011 +3
-5 1011 -5 1011
0100 +4 0100 +4
1010 1010
-6 0101 -6 0101
1001
+5 +5
0110 1001 0110
-7 1000 0111 +6 -7 1000 +6
0111
-8 +7 -8 +7

5 + 3 = -8 -7 - 2 = +7
Overflow Conditions
0111 1000
5 0101 -7 1001
3 0011 -2 1100
-8 1000 7 10111
Overflow Overflow
0000 1111
5 0101 -3 1101
2 0010 -5 1011
7 0111 -8 11000
No overflow No overflow
Overflow when carry-in to the high-order bit does not equal carry out
Characters
 In addition to numbers, computers
must be able to handle nonnumeric
text information consisting of
characters.
 Characters can be letters of the
alphabet, decimal digits, punctuation
marks, and so on.
 They are represented by codes

that are usually eight bits long.

 American Standards Committee on
Information Interchange (ASCII) code is
ASCII Table
Memory Locations,
and
Addresses
Memory Locations and
Addresses
n bits
first word
 Memory
second word
consists of
many millions of
•
storage cells, •
•
each of which
can store 1 bit. i th word
 Data is usually
accessed in n- •
bit groups •
•
called words.
 n is called last word
word length.
Figure 2.5. Memory words.
Memory Locations and
Addresses..
 32-bit
word length
32 bits
example
b31 b30 b1 b0

••
•
Sign bit: b31= 0 for positive numbers
b31= 1 for negative numbers

(a) A signed integer

8 bits 8 bits 8 bits 8 bits

ASCII ASCII ASCII ASCII

character character character character
(b) Four characters
Memory Locations and
Addresses..
 To retrieve information from memory, either
for one word or one byte (8-bit), addresses
for each location are needed.
 A k-bit address memory has 2k memory
locations, namely 0 – 2k-1, called memory
space.
 24-bit memory: 224 = 16,777,216 = 16M
(1M=220)
 32-bit memory: 232 = 4G (1G=230)
 1K(kilo)=210
 1T(tera)=240
Byte Addressability
 A byte is always 8 bits, but the word length
typically ranges from 16 to 64 bits.
 It is impractical to assign distinct
addresses to individual bit locations in
the memory.
 The most practical assignment is to have
successive addresses refer to successive byte
locations in the memory – byte-addressable
memory.
 Byte locations have addresses 0, 1, 2, … If
word length is 32 bits, they successive words
are located at addresses 0, 4, 8,…
Big-Endian and Little-Endian
Assignments
Big-Endian: lower byte addresses are used for the most significant bytes of
the word
Little-Endian: opposite ordering. lower byte addresses are used for the less
significant
bytes of the word Byte address
address Byte address
Word
0 0 1 2 3 0 3 2 1 0

4 4 5 6 7 4 7 6 5 4

• •
• •
• •

k k k k k k k k k k
2 -4 2 -4 2 -3 2 - 2 - 2 - 4 2 - 2 - 2 -3 2 -
2 1 1 2 4

(a) Big-endian assignment (b) Little-endian assignment

Figure 2.7. Byte and word addressing.

Word Alignment
 Address ordering of bytes
 Word alignment
 Words are said to be aligned in memory if
they begin at a byte address. that is a
multiple of the num of bytes in a word.
 16-bit word: word addresses: 0, 2, 4,….
 32-bit word: word addresses: 0, 4, 8,….
 64-bit word: word addresses: 0, 8,16,….
Accessing numbers, characters,
and character strings
 A number usually occupies one word.
 It can be accessed in the memory by
specifying its word address.
 Similarly, individual characters can be
accessed by their byte address.
 It is necessary to handle character
strings of variable length.
 The beginning of the string is indicated by
giving the
address of the byte containing its first
character.
 Successive byte locations contain
successive characters of the string.
Accessing numbers, characters,
and character strings..
 Thereare two ways to indicate the
length of the string.
 A special control character with the
meaning "end of string" can be used
as the last character in the string.
 Or a separate memory word location
or processor register can contain a
number indicating the length of the
string in bytes.
Memory Operations
 Load (or Read or Fetch)
 Copy the content. The memory content
doesn’t change.
 Address – Load
 Registers can be used
 Store (or Write)
 Overwrite the content in memory
 Address and Data – Store
 Registers can be used
Floating-Point Numbers and
Operations
 In the 2’s complement system, the signed

𝐹, represented by the 𝑛-bit binary

value

fraction
𝐵2=
𝐹 𝐵 = −𝑏0 × 𝑏0
0+ 𝑏
−1. ×
𝑏2−1 𝑏−2−2…× 𝑏
−1 + 𝑏 2−−2 + ⋯ +
𝑛−1 × 2− 𝑛−1

𝐹 −1 ≤ 𝐹 ≤ 1 − 2
𝑏− 𝑛−1 − 𝑛−1
where the
is given by range of is

approximately 0 to
 For 32-bit format, the range is

± 2.15 × 109 for integers and ±4.55 ×

10−10 to
± 1 for fractions.
IEEE Standard for Floating-
Point Numbers
A binary floating-point number
can be represented by
 A sign for the number
 Some significant bits

 A signed scale factor exponent for an

implied base of 2
 The basic IEEE format is a 32-bit
representation, shown in Figure 6.24a
 Based on 2008 version of IEEE (Institute of
Electrical and Electronics Engineers) Standard
754, labelled 754-2008
IEEE Standard for Floating-
Point Numbers..
 The leftmost bit represents the sign, 𝑆,

 The next 8 bits, 𝐸′, represent the

for the number.

signed exponent of the scale factor

 The remaining 23 bits, 𝑀, are the

(with an implied base of 2)

fractional part of the significant bits.

IEEE Standard for Floating-
Point Numbers..
 The full 24-bit string, B, of significant
bits, called the mantissa, always has a
leading 1, with the binary point
immediately to its right.
 Therefore, the mantissa

𝐵 = 1. 𝑀 = 1. 𝑏−1𝑏−2 … 𝑏−23
has the value
V 𝐵 = 1+ 𝑏−1 × 2−1 + 𝑏−2 × 2−2 + ⋯ + 𝑏−23 ×
2−23
 By convention, when the binary point
IEEE Standard for Floating-
Point Numbers..

exponent, 𝐸, the value stored in the

 Instead
of the actual signed

𝐸′ = 𝐸 + 127.
exponent field is an unsigned integer

 𝐸′ is in the range 0 ≤ 𝐸′ ≤ 255.

 This is called the excess-127 format.

 Theuse of the excess-127

representation for exponents
simplifies comparison of the relative
sizes of two floating-point numbers.
IEEE Standard for Floating-
Point Numbers..
 32-bit representation – single-
 8-bit excess-127 exponent 𝐸′ with 𝐸′ ≤
range 1
precision
≤
254 for normal values

127 providing scale factors of 2−126 to 2127

𝐸′, is in the range ≤ 𝐸′
 0 and 255 indicate special values
(approximately 10±38).
−126 ≤
 The actual exponent,
 The 54-bit mantissa provides a precision
equivalent to
about 7 decimal digits
IEEE Standard for Floating-
Point Numbers..
 64-bit representation – double-precision
11-bit excess-1023 exponent 𝐸′ with
range 1


≤
𝐸′ ≤ 2046 for normal values

The actual exponent, 𝐸′, is in the range

 0 and 2047 indicate special values


of 2−1022 to 21023(approximately 10±308).

−1022 ≤ E ≤ 1023, providing scale factors

 The 53-bit mantissa provides a

precision equivalent to about 16
IEEE Standard for Floating-
Point Numbers..
IEEE Standard for Floating-
Point Numbers..
 Two basic aspects of operating with
floating- point numbers
 First, if a number is not normalized, it

can be put in normalized form by

shifting the binary point and adjusting
the exponent.
 Underflow
 Second, as computations proceed, a
number that does not fall in the
representable range of normal
Special Values

excess-127 exponent 𝐸′ are used to

 The end values 0 and 255 of the

represent special values.

 When 𝐸′ = 0 and 𝑀 = 0, the value 0 is

When 𝐸′ = 255 and 𝑀 = 0, the

represented.

value ∞ is represented.


 When 𝐸′ = 0 and 𝑀 ≠ 0, denormal

When 𝐸′ = 255 and 𝑀 ≠ 0, the value

numbers are represented.


represented is called Not a Number (NaN).

Instructions & Instruction Sequencing
“Must-Perform” Operations
A computer must have instructions
capable of performing four types of
operations:
 Data transfers between the memory
and the processor registers
 Arithmetic and logic operations on
data
 Program sequencing and control
 I/O transfers
Register Transfer Notation
 Identify a location by a symbolic name
standing for its hardware binary address
 Names for addresses of memory location
may be LOC, PLACE, A, VAR2
 Processor register names may be R0, R5
 I/O register names may be DATAIN,
OUTSTATUS
 Contents of a location are denoted by
placing square brackets around the name
of the location
 R1←[LOC]
 R3 ←[R1]+[R2]
Assembly Language Notation
 Represent machine instructions
and programs.
 Move LOC, R1 = R1←[LOC]

 Add R1, R2, R3 = R3 ←[R1]+

[R2]
CPU Organization
 Single Accumulator
 Result usually goes to the Accumulator
 Accumulator has to be saved to
memory quite often
 General Register
 Registers hold operands thus reduce
memory traffic
 Register bookkeeping
 Stack
 Operands and result are always in the
stack
Basic Instruction Types
 Three-Address Instructions
 Add R1, R2, R3 R3 ←
R1 + R2
 Two-Address Instructions
 Add R1, R2 R2 ← R1 + R2
 One-Address
 Add M Instructions AC ← AC +
 Zero-Address [M]
Instructions TOS ← TOS + (TOS –
 Add 1)
 RISC
 LotsInstructions
of registers. Memory is restricted to Load
& Store
Opcode Operand(s) or Address(es)
Basic Instruction Types..
Example: Evaluate (A+B) 
(C+D)
Three-Address
 1. Add A, B, R1 ; R1 ← [A] +
2. Add C, D, R2 [B]
3. Multipl R1, R2, ; R2 ← [C] +
y [D]
X
; X ← [R1] 
[R2]
Basic Instruction Types..
Example: Evaluate (A+B) 
(C+D)
 Two-Address

1. Move A, R1 ; R1 ← [A]
2. Add B, R1 ; R1 ← [R1] +
[B]
3. Move C, R2 ; R2 ← [C]
4. Add D, R2 ; R2 ← [R2] +
[D]
5. Multiply R1, R2 ; R2 ← [R1] 
[R2]
6. Move R2, X ; X ← [R2]
Basic Instruction Types..
Example: Evaluate (A+B) 
(C+D)
One-Address
 1. Load ; AC ← A
A ; AC ← AC + B
2. Add ; T ← AC
B ; AC ← [C]
3. Store ; AC ← AC +
T [D]
4. Load ; AC ← AC 
C [T]
5. Add ; X ← AC
D
 Basic Instruction Types..
Example: Evaluate (A+B) 
(C+D)
Zero-Address
 1. Push ; TOS ← A
A ; TOS ← B
2. Push ; TOS ← (A + B)
B ; TOS ← C
3. Add ; TOS ← D
4. Push ; TOS ← (C + D)
C
; TOS ←
5. Push (C+D)(A+B)
D X
; X ← TOS
6. Add
Basic Instruction
Types..
 RISC
Example: Evaluate (A+B) 
(C+D)
1. A, R1 ; R1 ← [A]
Load
2. B, R2 ; R2 ← [B]
Load
3. C, R3 ; R3 ← [C]
Load
4. D, R4 ; R4 ← [D]
Load
5. Add R1, R2 ; R2 ← R1 +
R2
6. Add R3, R4 ; R4 ← R3 +
R4
Using Registers
 Registers are faster
 Shorter instructions
 The number of registers is smaller, only
few bits are needed to specify the
register (e.g. 32 registers need 5 bits)
 Potential speedup
 Minimize the frequency with which

data is moved back and forth

between the memory and processor
registers.
 Instruction Execution and
Straight-Line Sequencing
Address Contents

i Move A,R0
Assumptions:
Begin execution here
3-instruction - One memory
i+4 Add B,R0 program
i+8 Move R0,C
segment operand per
instruction
- 32-bit word length
- Memory is byte
A addressable
- Full memory
address can be
B Data for directly specified
the program
in a single-word
Two-phase
instruction
procedure
-Instruction fetch
C
-Instruction
execute
Page 43
Figure 2.8. A program for C   + 
 i Move NUM1,R0

i+4 Add NUM2,R0

Branching i+8 Add NUM3,R0

•
•
•
Add NUM n,R0
i + 4n - 4
Move R0,SUM
i + 4n

•
•
•
SUM
NUM1
NUM2

•
•
•
NUM n

Figure 2.9. A straight-line program for adding n numbers.

 Move N,R1
Clear R0

Branching LOOP
Determine address of
"Next" number and add
Program "Next" number to R0
loop
Decrement R1
Branch>0 LOOP
Branch target
Move
R0,SUM
Conditional
branch •
•
•
SUM
N n
NUM1

Figure 2.10. Using a loop to add n numbers. NUM2

•
•
•
NUM n
Condition Codes
 The processor keeps track of
information about the results of
various operations for use by
subsequent conditional branch
instructions.
 Accomplished by recording the required
information in individual bits, often called
condition code flags.
 These flags are usually grouped
together in a special processor register
called the condition code register or
Condition Codes
 Four commonly used flags are
 N (negative)
 Set to 1 if the result is negative; otherwise, cleared
to 0
 Z (zero)
 Set to 1 if the result is 0; otherwise, cleared to 0
 V (overflow)
 Set to 1 if arithmetic overflow occurs; otherwise,
cleared to 0
 C (carry)
 Set to 1 if a carry-out results from the operation;
otherwise, cleared to 0
Status Bits

Cn-1 A B

Cn ALU
F
V Z N C
Fn-1

Zero Check