Chapter 9

Logic Families and Their Characteristics

By: MSc .Muneera Altayeb

 Outline
 Bipolar Logic Families
 Unipolar Logic Families
 The TTL Family
 TTL Voltage and Current Ratings
 Other TTL Considerations
 Improved TTL Series
 The CMOS Family
 Emitter-Coupled Logic (ECL)
 Comparing Logic Families
 Interfacing Logic Families

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 Digital Logic Families
 Bipolar Logic Families:
1. Diode logic (DL)
No longer
2. Diode–transistor logic (DTL) used
3. Resistor–transistor logic (RTL)
4. Transistor-transistor logic (TTL).
5.Emitter-Coupled Logic (ECL)
 Unipolar Logic Families:
1. Complementary metal oxide
semiconductor(CMOS)
2. P-channel MOSFETs (PMOS)
3. N-channel MOSFETs(NMOS)
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 Subfamilies within each family
Different speed, power consumption, voltage
and current levels, and temperature ranges
There are standardized numbering
schemes but prefixes may differ

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 Diode logic (DL)
Diode logic level :
Logic 1 (3-5)v
Logic 0 (0-2)v

AND logic gate

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 Diode–transistor logic (DTL)
Diode-transistor logic level :
Logic 1 (2.4-5)v
Logic 0 (0-0.4)v

NAND logic gate

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 Diode–Transistor Logic (DTL)

Fig.4.12 A 3-input DTL NAND gate driving N similar gates.

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 The TTL Family
NPN bipolar transistor
Physical model
Schematic symbol
Diode equivalent

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 The TTL Family
Inverter
Two-input NAND gate
Multi-emitter transistor
Totem-pole output stage
HIGH level output typically 3.4 V
LOW level output typically 0.2 V

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 The TTL Family
Figure 2.37 Schematic of a TTL inverter (7404) circuit.

 Q4 replaces Rc, acts in

opposite to Q3.
 Such combination is called the
totem-pole arrangement.
 Q1 (input transistor) drives
Q2.

 D1 protects Q1 from negative

voltages at input.
 D2 ensures that Q4 cuts off
totally when Q3 AisPractical
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 A 7404 TTL IC chip is called 14 pin
DIP( Dual-in-line package)

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 The TTL Family
7400 two-input NAND gate

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 TTL Voltage and Current
Ratings
Input/output current
Source current – IOH
Sink current + IOL
Low-level input current – IIL
High level input current – IIH

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 Main Characteristics of Logic
Families
Fan-out.
Noise Margin .
Propagation Delay .
Power Dissipation .

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 TTL Voltage and Current
Ratings
Fan-out is the number
of gate inputs of the
same sub-family that
a single output can
drive.

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 TTL Voltage and Current
Ratings
Example of TTL gate sinking input currents
from two gate inputs using logic symbols

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 TTL Voltage and Current Ratings
Example of TTL gate sinking input currents
from two gate inputs using schematic
symbols

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 TTL Voltage and Current
Ratings
Example of TTL gate sourcing current to
two gate inputs using logic symbols

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 TTL Voltage and Current Ratings
Example of TTL gate sourcing current to
two gate inputs using schematic
symbols

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 TTL Voltage and Current Ratings
Summary of I/O current and fan-
out:
Low-level input current I = -1.6 mA (-1600 μA)
IL
High level input current I = 40 μA
IH
 (The minus sign indicates current leaving the gate)
I – low-level output current = 16 mA (16,000 μA)
OL
I – high-level output current = -400 μA (-800 μA
OH
for some)
Fan-out is max number of gate inputs that can be
connected to a standard TTL gate output.
 Typically fan-out = 10.
Note: Current ratings are not the amount of
current, but Athe
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 NOR gate in the standard TTL

Figure 5.9 NOR gate in the standard TTL.

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 Example 5.5
Refer to Fig. 5.30. Determine the current being
sourced by gate 1 when its output is HIGH and
sunk by it when its output is LOW. All gates are
from the standard TTL family, given that I IH =
40A and IIL= 1.6 mA.

Fig. 5.30

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 Solution
• When the output is HIGH, the inputs of all gates draw current
individually.
• Therefore, the input loading factor=equivalent of seven gate
inputs=7 × 40 A=280 A.
• The current being sourced by the gate 1 output=280 A.
• When the output is LOW, shorted inputs of AND and NAND gates
offer a load equal to that of a single input owing to a multi-emitter
transistor at the input of the gate. The inputs of OR and NOR
gates draw current individually on account of the use of separate
transistors at the input of the gate.
• Therefore, the input loading factor=equivalent of five gate
inputs=5 × 1.6=8 mA.
• The current being sunk by the gate 1 output=8 mA.

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 TTL Voltage and Current Ratings
Input/Output Voltages (graphical
representation)

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 Noise Margin

Noise margin: The difference between high level

voltages and low level voltages

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 TTL Voltage and Current Ratings
Input/Output Voltages and noise margin

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 Discussion Point
Locate the voltage and current ratings
covered so far on the following typical data
sheet (Figure 9.8).

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 Pulse-Time Parameters
Rise Time (tr) – Measured from 10% level to
90% level
Fall Time (tf) – Measured from 90% level to
10% level

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 Propagation Delay
Propagation Delay (tPLH and tPHL)
Determined by transistor switching speed

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 Power Dissipation
Total power supplied to the IC power supply
terminals
Assume 50% duty cycle.
PD = VCC x ICC(av)

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 Open-Collector Outputs
Upper transistor is removed
Can sink current but cannot source current

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 Open-Collector Outputs
To get a TTL OC output or a CMOS OD output
to produce a HIGH, a pull-up resistor is
required.

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 Wired-output operation
Outputs from two or more gates tied
together
Wired-AND logic

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 Other TTL Considerations
Disposition of unused inputs and unused
gates:
Open inputs degrade noise immunity
AND and NAND – tied HIGH
OR and NOR – tied to ground
Unused gates – force outputs HIGH

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 Other TTL Considerations
Power supply decoupling
TTL logic tends to produce spikes on the VCC
line
Connecting a 0.01 to 0.1 F capacitor
between VCC and ground pins
 Reduces EMI radiation
 Reduces effect of voltage spikes from power supply

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 Schottky TTL
Main speed limitation of standard TTL is
due to capacitive charge in transistor base.
Charge is stored when saturated
74SXX TTL series adds a Schottky diode
between the base and collector.

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 Schottky TTL
Lower-power Schottky (LS)
Power consumption significantly reduced
Speed-power product 1/3 of 74SXX series
and 1/5 of 74XX series
Advanced low-power Schottky (ALS)
Propagation delay dropped from 9 to 4 ns
Power dissipation from 2 to 1 mW per gate
More expensive
Fast (F)
Propagation lowered to under 3 ns.
Device size dramatically reduced

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 The CMOS Family
MOSFETs
Metal oxide semiconductor field-effect
transistors
High input impedance and low power
dissipation

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 The CMOS Family
Three major MOS families
PMOS: P-channel
NMOS: N-channel
CMOS: Complimentary P- and N-channel

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 The CMOS Family
CMOS inverter formed from N-and P-
channel MOSFETS.

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 Figure 2.42 A 4049 CMOS hex inverter
pin configuration.

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 Other CMOS Gates

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 CMOS Transmission Gate

53 Modern Digital Electronics by RP Jain 4th ed

 CMOS considerations
Since MOS devices have very high input
impedance, therefore, the fan-out is large.
The propagation delay time is large in MOS
devices because of large capacitances
present at the input and output of these
devices. Also, the resistance through which
these capacitors get charged and
discharged is high.

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 Handling CMOS devices
Avoid electrostatic discharge
Ground work station, test equipment and
soldering irons
Wear a wrist strap
Don’t connect input signals with power off
Connected unused inputs to VDD
Don’t remove IC with power on

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 CMOS Availability
4000 series - original CMOS line
40H00 series - faster
74C00 series - pin compatible with TTL
74HC00 and 74HCT00 series
Speedy, less power, pin compatible, greater
noise immunity and temperature operating
range

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 CMOS Availability
74- BiCMOS series - low power and high
speed
74-Low Voltage series
See appendix B
Nominal supply voltage of 3.3 V
74AHC and 74AHCT series
Superior speed
Low power consumption
High output drive current

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 CMOS Availability
74AVC advanced very-low-voltage CMOS
logic
Faster speed (maximum 2 ns)
Very low operating voltages
 3.3 V, 2.5 V, 1.8 V, 1.5 V and 1.2 V
Dynamic output control
 Adjusts output impedance to minimize overshoot
and undershoot

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 Emitter-Coupled Logic (ECL)
Extremely fast
Increased power dissipation
Uses differential amplifiers

Figure 9-22
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 Fig. 4.19
A 3-input ECL OR/NOR gate.

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 Developing Technologies
Newer technologies
Integrated injection logic (I2L)
Silicon-on-sapphire (SOS)
Gallium arsenide (GaAs)
Josephson junction circuits
In all cases the goal is higher frequencies
and increased density.

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 Comparing Logic Families
Performance specifications

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 Comparing Logic Families
Propagation delay versus power

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 Interfacing Logic Families
TTL to CMOS

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 Interfacing Logic Families
TTL to CMOS
Pull-up resistor

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 Interfacing Logic Families
CMOS to TTL

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 Interfacing Logic Families
CMOS to TTL

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 Interfacing Logic Families

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 Interfacing Logic Families
Level Shifting
Level-shifter IC: 4050B

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 Interfacing Logic Families
Level Shifting
Level-shifter IC: 4504B

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 Interfacing Logic Families
ECL Interfacing

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 Summary
There are three stages of internal circuitry in a
TTL IC: input, control, and output.
The input current to an IC gate is a constant
value specified by the manufacturer.
The output current of an IC gate depends on
the size of the load connected to it. Its value
cannot exceed the maximum rating of the
chip, IOL or IOH.

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 Summary
The HIGH- and LOW-level output voltages of
the standard TTL family are not 5 V and 0 V
but typically are 3.4 V and 0.2 V.
The propagation delay is the length of time
that it takes for the output of a gate to
respond to a stimulus at its input.
The rise and fall times of a pulse describe how
long it takes for the voltage to travel between
its 10% and 90% levels.

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 Summary
Open-collector outputs are required
whenever logic outputs are connected to a
common point.
Several improved TTL families are available
and continue to be introduced each year
providing decreased power consumption
and decreased propagation delay.

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 Summary
The CMOS family uses complementary
metal oxide semiconductor transistors
instead of the bipolar transistors used in
TTL ICs. Traditionally, the CMOS family
consumed less power but was slower than
TTL. However, recent advances in both
technologies have narrowed the
differences.

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 Summary

The BiCMOS family combines the best

characteristics of bipolar technology and
CMOS technology to provide logic functions
that are optimized for the high-speed, low-
power characteristics required in
microprocessor systems.

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 Summary
Emitter-coupled logic (ECL) provides the
highest-speed ICs. Its drawback is its very
high power consumption.
A figure of merit of IC families is the
product of their propagation delay and
power consumption, called the speed-
power product (the lower, the better).

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 Summary
When interfacing logic families, several
considerations must be made. The output
voltage level of one family must be high
and low enough to meet the input
requirements of the receiving family. Also,
the output current capability of the driving
gate must be high enough for the input
draw of the receiving gate or gates.

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 References
Digital Electronics A Practical
Approach ,William Kleitz,Pearson,7th Ed
2004
Modern Digital Electronics by RP Jain 4 th ed
Digital Electronics: Principles, Devices and
Applications Anil K. Maini 2007

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