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CE Configurations

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Lawrence Ramos
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0% found this document useful (0 votes)
15 views

CE Configurations

Uploaded by

Lawrence Ramos
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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BJT Biasing and Direct

Current Analysis
Part 1
(Transistor Operating Points, Common-Emitter Configuration, Fixed Bias,
Emitter Bias, Voltage-Divider Bias, Collector-Feedback)
TRANSISTOR OPERATING
POINTS
• For transistor amplifiers the resulting dc current and voltage establish
an operating point on the characteristics that define the region that
will be employed for amplification of the applied signal.
• Because the operating point is a fixed point on the characteristics, it is
also called the quiescent point (Q-point). By definition, quiescent
means quiet, still, inactive.
Various operating points
within the limits of operation
of a transistor
Various operating points within the
limits of operation of a transistor
• The BJT device could be biased to operate outside these maximum limits, but the result
of such operation would be either a considerable shortening of the lifetime of the
device or destruction of the device.
• Confining ourselves to the active region, we can select many different operating areas
or points. The chosen Q-point often depends on the intended use of the circuit.

• Operation in the cutoff, saturation, and linear regions of the BJT characteristic are
provided as follows:
1) Linear-region operation: Base–emitter junction forward-biased Base–collector
junction reverse-biased
2) Cutoff-region operation: Base–emitter junction reverse-biased Base–collector
junction reverse-biased
3) Saturation-region operation: Base–emitter junction forward-biased Base–collector
junction forward-biased
Common-Emitter
Configurations
Fixed Bias Configuration
Fixed Bias Configuration
• The fixed-bias circuit is the simplest transistor dc bias configuration. Even though
the network employs an npn transistor, the equations and calculations apply
equally well to a pnp transistor configuration merely by changing all current
directions and voltage polarities. The current directions of are the actual current
directions, and the volt- ages are defined by the standard double-subscript
notation.
• For the dc analysis the network can be isolated from the indicated ac levels by
replacing the capacitors with an open-circuit equivalent because the reactance of
a capacitor is a function of the applied frequency. For dc, f = 0 Hz, and XC = 1 /
[2*pi*f*C] = 1 / [2*pi*0*C] = ¥ W. In addition, the dc supply VCC can be separated
into two supplies (for analysis purposes only) to permit a separation of input and
output circuits. It also reduces the linkage between the two to the base current IB.
• The separation is certainly valid, as we note that VCC is connected directly to RB
and RC.
Fixed Bias Configuration
Transistor Saturation
• The term saturation is applied to any system where
levels have reached their maximum values.
• For a transistor operating in the saturation region, the
current is a maximum value for the particular design.
Change the design and the corresponding saturation
level may rise or drop.
• Of course, the highest saturation level is defined by
the maximum collector current as provided by the
specification sheet.
• Saturation conditions are normally avoided because
the base–collector junction is no longer reverse-biased
and the output amplified signal will be distorted.
Load-Line Analysis
• In load-line analysis, the load (network resistors) of the network defines the slope of the straight line
connecting the points defined by the network parameters.
• The characteristics of the BJT are superimposed on a plot of the network equation defined by the same
axis parameters. The load resistor RC for the fixed-bias configuration will define the slope of the
network equation and the resulting intersection between the two plots.
• The smaller the load resistance, the steeper the slope of the network load line.
Emitter Bias
Voltage-Divider Bias
• There are two methods that can be
applied to analyze the voltage-divider
configuration.
• The first is the exact method, which can
be applied to any voltage-divider
configuration.
• The second is referred to as the
approximate method and can be applied
only if specific conditions are satisfied.
• The approximate approach permits a
more direct analysis with a savings in time
and energy.
Advantage of Voltage Divider
• Voltage divider biasing is commonly used because of the main reason
that the transistor under this biasing always remains in the active
region(the emitter-base junction is always forward biased).
• Because Voltage divider biasing is beta-independent and hence is
more stable than any other biasing.
Exact Analysis
• For the dc analysis the network of Figure below, we transform the input terminal
into its Thévenin equivalent circuit.
Get for the
Get the
Replace the circuit
Approximate Analysis
• The input section of the voltage-divider
configuration can be represented by the
network of Figure shown.
• The resistance Ri is the equivalent
resistance between base and ground for
the transistor with an emitter resistor RE.
• The reflected resistance between base
and emitter is defined by Ri = ( + 1)RE.
• If Ri is much larger than the resistance ,
the current will be much smaller than
(current always seeks the path of least
resistance) and will be approximately
equal to .
Approximate Analysis
• If we accept the approximation that IB is essentially 0 A compared to or ,
then , and and can be considered series elements.
• The voltage across , which is actually the base voltage, can be determined
using the voltage-divider rule (hence the name for the configuration).

• If this condition is satisfied, then:


Approximate Analysis
• Transistor Saturation. The output collector–emitter circuit for the
voltage-divider configuration has the same appearance as the emitter-
biased circuit. The resulting equation for the saturation current (when
VCE is set to 0 V on the schematic) is therefore the same as obtained
for the emitter-biased configuration.
Collector-Feedback
• An improved level of stability can also be
obtained by introducing a feedback path from
collector to base as shown in the figure.
• Although the Q-point is not totally independent
of beta (even under approximate conditions),
the sensitivity to changes in beta or
temperature variations is normally less than
encountered than the fixed-bias or emitter-
biased configurations.

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