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Lecture 2 - Adders - Multipliers

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Lecture 2 - Adders - Multipliers

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ssarugeshkl
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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23AD304

COMPUTER ARCHITECTURE
AND ORGANIZATION
Dr E Emerson Nithiyaraj
AP/ECE
UNIT II
ARITHMETIC UNIT
Dr E Emerson Nithiyaraj
AP/ECE
Positive values have
identical representations in
all systems, but negative
values have different
representations.

In the sign-and-
magnitude system,
negative values are
represented by changing
the MSB (b3 in Figure 1.3)
from 0 to 1 in the B vector
of the corresponding
positive value.
In 1’s-complement
representation, negative
values are obtained by
complementing each bit of
the corresponding positive
number.

The 2’s-complement of a
number is obtained by
adding 1 to the 1’s-
complement of that
number.
• The sign-and-magnitude system is the simplest representation, but it is also
the most awkward for addition and subtraction operations.

• The 1’s-complement method is somewhat better.

• The 2’s-complement system is the most efficient method for performing


addition and subtraction operations.
The rules governing addition and subtraction of n-bit signed numbers using the 2’s
complement representation system may be stated as follows:
In all of these 4-bit examples, the answers fall within the representable range of −8
through +7. When answers do not fall within the representable range, we say that
arithmetic overflow has occurred.
Since the carries must propagate, or ripple, through this cascade, the
configuration is called a ripple-carry adder.
The carry signals are also useful for interconnecting k adders to form an adder
capable of handling input numbers that are kn bits long, as shown in Figure 9.2c.
Arithmetic overflow occurs when the signs of the two operands are the same,
but the sign of the result is different. Therefore, a circuit to detect overflow can
be added to the n-bit adder by implementing the logic expression
The logic
circuit shown in
Figure 9.3 can
be used to
perform either
addition or
subtraction
based on the
value applied to
the Add/Sub
input control
line
• The delay through a network of logic gates depends on the integrated circuit
electronic technology used in fabricating the network and on the number of
gates in the paths from inputs to outputs.

• The delay through any combinational circuit constructed from gates in a


particular technology is determined by adding up the number of logic-gate
delays along the longest signal propagation path through the circuit.
Since the carries must propagate, or ripple, through this cascade, the
configuration is called a ripple-carry adder.
Carry Propagation
• The total propagation time is equal to the propagation delay of a
typical gate, times the number of gate levels in the circuit.
• The longest propagation delay time in an adder is the time it takes
the carry to propagate through the full adders.
• Since each bit of the sum output depends on the value of the input
carry, the value of Si at any given stage in the adder will be in its
steady-state final value only after the input carry to that stage has been
propagated.
• Thus, only after the carry propagates and ripples through all stages will
the last output S3 and carry C4 settle to their final correct value.
Carry Propagation
• The carry propagation time is an important attribute of the adder
because it limits the speed with which two numbers are added.

• An obvious solution for reducing the carry propagation delay time


is to employ faster gates with reduced delays.

• There are several techniques for reducing the carry propagation time in
a parallel adder. The most widely used technique employs the principle
of Carry Lookahead Logic.
• Two approaches can be taken to reduce delay in adders.

• The first approach is to use the fastest possible electronic technology.

• The second approach is to use a logic gate network called a carry-


lookahead network, which is described in the next section.
If Gi = 1, Ci+1 = 1
independent of the input
carry, provided xi and yi =
1.

Pi = 1 when either xi and


yi = 1
• Gi is called a carry generate , and it produces a carry of 1 when both
xi and yi are 1, regardless of the input carry ci.

• Pi is called a carry propagate, because it determines whether a carry


into stage i will propagate into stage i + 1
x y
Gi = xiyi
If we try to extend the carry-lookahead adder design of Figure 9.4b for longer
operands, we encounter the problem of gate fan-in constraints.
So the adder design shown in Figure 9.4b cannot be extended easily for longer operands.
However, it is possible to build longer adders by cascading a number of 4-bit adders,
as shown in Figure 9.2c
M
Q

P
• The combinational array multiplier just described uses a large number of
logic gates for multiplying numbers of practical size, such as 32- or 64-
bit numbers.

• Multiplication of two n-bit numbers can also be performed in a


sequential circuit that uses a single n-bit adder.
When we add a negative
multiplicand to a partial
product, we must extend the
sign-bit value of the
multiplicand to the left as
far as the product will
extend.
• For a negative multiplier, a straightforward solution is to form the 2’s-
complement of both the multiplier and the multiplicand and proceed as in
the case of a positive multiplier.

• This is possible because complementation of both operands does not


change the value or the sign of the product. A technique that works equally
well for both negative and positive multipliers, called the Booth algorithm,
is described next.
• A technique called bit-pair recoding of the multiplier results in using at
most one summand for each pair of bits in the multiplier.
Convert ‘Q’ bits Multiplier bits
into one bit
recoded ‘Q’ bits. Left most – sign bit
From those, find appended
bit-pair recoded
values Right most – 0 appended
1. Difference Multiplier bits
between adjacent
bits Left most – sign bit
appended
One-bit recorded
values Right most – 0 appended
2. Find bit-pair Multiplier bits
recorded values
Left most – sign bit
Bit-pair recorded appended
values
Right most – 0 appended
Multiplier bits
11010
One- Bit
Recoding If Multiplier bit is -1, 2’s
Technique complement of Multiplicand.

If Multiplier bit is +1, same bits


are repeated.

If Multiplier bit is +2,


multiplicand × (+2) = M × (10).

If Multiplier bit is -2, 2’s


complement of multiplicand ×
(+2) = 2’s (M) × (10).

6 summands
Two - Bit Multiplier bits
Recoding 11010
Technique If Multiplier bit is -2, (-2M). Written
as 2’s complement value and start
from 21 position. So, keep 20
position as 0 value.

If Multiplier bit is -1, (-1M). Written


as 2’s complement value and start
from 20 position.

3 summands
M
Q
• The delay through the carry-save array is somewhat less than the delay
through the ripple-carry array. This is because the S and C vector outputs
from each row are produced in parallel in one full-adder delay.
• The interconnection pattern between levels in a CSA tree that uses 3-2 reducers
is irregular.
• A more regularly structured tree can be obtained by using 4-2 reducers,
especially for the case in which the number of summands to be reduced is a
power of 2.
• For example, if 32 summands are reduced to 2 using 4-2 reducers at each
reduction level, then only four levels are needed. The tree has a regular
structure, with 16, 8, 4, and 2 summands at the outputs of the four levels. If 3-2
reducers are used, eight levels are required, and the wiring connections between
levels are quite irregular.
• Restoring Division

• Non-Restoring Division
n M A Q Action
4 00011 00000 1011 Initial
n M A Q Action
4 00011 00000 1011 Initial

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