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6 views

ch2 c55x 1

PPT

Uploaded by

hema
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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TI C55x instruction set

C55x programming model.


C55x assembly language.
C55x memory organization.
C55x data operations.
C55x flow of control.

Overheads for Computers as


© 2008 Wayne Wolf Components 2nd ed.
TI C55x overview

Accumulator architecture:
 acc = operand op acc.
 Very useful in loops for DSP.
C55x assembly language:
MPY *AR0, *CDP+, AC0
Label: MOV #1, T0
C55x algebraic assembly language:
AC1 = AR0 * coef(*CDP)
Overheads for Computers as
© 2008 Wayne Wolf Components 2nd ed.
Intrinsic functions

Compiler support for assembly


language.
Intrinsic function maps directly onto
an instruction.
Example:
 int_sadd(arg1,arg2)
 Performs saturation arithmetic addition.

Overheads for Computers as


© 2008 Wayne Wolf Components 2nd ed.
C55x data types

Data types:
 Word: 16 bits.
 Longword: 32 bits.
Instructions are byte-addressable.
Some instructions operate on
register bits.

Overheads for Computers as


© 2008 Wayne Wolf Components 2nd ed.
C55x registers

Terminology:
 Register: any type of register.
 Accumulator: acc = operand op ac.
Most registers are memory-mapped.

Overheads for Computers as


© 2008 Wayne Wolf Components 2nd ed.
C55x program counter and
control flow registers

PC is program counter.


XPC is program counter extension.
RETA is subroutine return address.

Overheads for Computers as


© 2008 Wayne Wolf Components 2nd ed.
C55x accumulators and
status registers

Four 40-bit accumulators: AC0, AC1,


AC2, and AC3.
 Low-order bits 0-15 are AC0L, etc.
 High-order bits 16-31 are AC0H, etc.
 Guard bits 32-39 are AC0G, etc.
ST0, ST1, PMST, ST0_55, ST1_55,
ST2_55, ST3_55 provide
arithmetic/bit manipulation flags, etc.
Overheads for Computers as
© 2008 Wayne Wolf Components 2nd ed.
C55x stack pointers

SP keeps track of user stack.


SSP holds system stack pointer.
SPH is extended data page pointer
for both SP and SSP.

Overheads for Computers as


© 2008 Wayne Wolf Components 2nd ed.
C55x auxiliary registers and
circular buffer pointers

AR0-AR7 are auxiliary instructions.


CDP points to coefficients for
polynomial evaluation instructions.
CDPH is main data page pointer.
BK47 is used for circular buffer
operations along with AR4-7.
BK03 addresses circular buffers.
BKC is size register for CDP.
Overheads for Computers as
© 2008 Wayne Wolf Components 2nd ed.
C55x block repeat registers

BRC0 counts block repeat


instructions.
RSA0L and REA0L keep track of start
and end points of blocks.
BRC1 and BRS1 are used to repeat
blocks of instructions.
RSA0 and RSA1 are the start address
registers for block repeats.
Overheads for Computers as
© 2008 Wayne Wolf Components 2nd ed.
C55x addressing mode and
interrupt registers

DP and DPH set base address for data


access.
PDP determines base address for I/O.
IER0 and IER1 are interrupt mask
registers.
IFR0 and IFR1 keep track of currently
pending registers.
DBIER0 and DBIER1 are for debugging.
Overheads for Computers as
© 2008 Wayne Wolf Components 2nd ed.
C55x memory map
 24-bit address space, memory mapped registers
main data page 0
16 MB of memory. main data page 1
 Data, program, I/O
main data page 2
all mapped to same
…
physical memory.
 Addressability:
 Program space
address is 24 bits. main data page 127
 Data space is 23 bits.
 I/O address is 16 bits.
Overheads for Computers as
© 2008 Wayne Wolf Components 2nd ed.
C55x addressing modes

Three addressing modes:


 Absolute addressing supplies an
address in an instruction.
 Direct addressing supplies an offset.
 Indirect addressing uses a register as a
pointer.

Overheads for Computers as


© 2008 Wayne Wolf Components 2nd ed.
C55x direct addressing

DP addressing accesses data pages:


 ADP = DPH[22:15](DP+Doffset)
SP addressing accesses stack values:
 ASP = SPH[22:15](SP+Soffset)
Register-bit direcdt addressing accesses
bits in registers.
PDP addressing accesses data pages:
 APDP = PDP[15:6]PDPoffset
Overheads for Computers as
© 2008 Wayne Wolf Components 2nd ed.
C55x indirect addressing
 AR indirect addressing uses auxiliary
register to point to data.
 Dual AR indirect addressing allows two
simultaneous accesses.
 CDP indirect addressing uses CDP to
access coefficients.
 Coefficient indirect addressing is similar to
CDP indirect but for instructions with 3
memory operands per cycle.
Overheads for Computers as
© 2008 Wayne Wolf Components 2nd ed.
C55x stack operations
Two stacks: data and system.
Three different stack configurations:
 Dual 16-bit stack with fast return has
independent data and system stacks.
 Dual 16-bit stack with slow return,
independent data and system stacks but
RETA and CFCT are not used for slow returns.
 32-bit stack with slow return, SP and SSP are
both modified by the same amount.

Overheads for Computers as


© 2008 Wayne Wolf Components 2nd ed.
C55x data operations
 MOV moves data between registers and
memory:
 MOV src, dst
 Varieties of ADDs:
 ADD src,dst
 ADD dual(LMEM),ACx,ACy
 Multiplication:
 MPY src,dst
 MAC AC,TX,ACy
Overheads for Computers as
© 2008 Wayne Wolf Components 2nd ed.
C55x flow of control

Unconditional branch:
 B ACx
 B label
Conditional branch:
 BCC label, cond
Loops:
 Single-instruction repeat
 Block repeat
Overheads for Computers as
© 2008 Wayne Wolf Components 2nd ed.
Efficient loops

General rules:
 Don’t use function calls.
 Keep loop body small to enable local
repeat (only forward branches).
 Use unsigned integer for loop counter.
 Use <= to test loop counter.
 Make use of compiler---global
optimization, software pipelining.
Overheads for Computers as
© 2008 Wayne Wolf Components 2nd ed.
Single-instruction repeat loop
example

STM #4000h,AR2
; load pointer to source
STM #100h,AR3
; load pointer to destination
RPT #(1024-1)
MVDD *AR2+,*AR3+
; move

Overheads for Computers as


© 2008 Wayne Wolf Components 2nd ed.
C55x subroutines

Unconditional subroutine call:


 CALL target
Conditional subroutine call:
 CALLCC adrs,cond
Two types of return:
 Fast return gives return address and loop
context in registers.
 Slow return puts return address/loop on
stack.
Overheads for Computers as
© 2008 Wayne Wolf Components 2nd ed.
C55x interrupts
Handled using subroutine mechanism.
Four step handling process:
 Receive interrupt.
 Acknowledge interrupt.
 Prepare for ISR by finishing current
instruction, retrieving interrupt vector.
 Processing the interrupt service routine.
32 possible interrupt vectors, 27
priorities.
Overheads for Computers as
© 2008 Wayne Wolf Components 2nd ed.

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