Chapter 3: Memory

Management
Chapter Outline
• Introduction
• Memory Allocation
• Segmentation
• Paging
• Structure of the Page Table
 Introduction

• Program must be brought (from disk) into memory and

placed within a process for it to be run
• Main memory and registers are only storage CPU can
access directly
• Memory unit only sees a stream of addresses + read
requests, or address + data and write requests
• Register access in one CPU clock (or less)
• Cache sits between main memory and CPU registers
• Protection of memory required to ensure correct
operation
 Base and Limit Registers
• A pair of base and limit registers define the logical address
space
• CPU must check every memory access generated in user mode
to be sure it is between base and limit for that user
 Logical vs. Physical Address Space

• The concept of a logical address space that is bound to a

separate physical address space is central to proper memory
management
• Logical address – generated by the CPU; also referred to as virtual
address
• Physical address – address seen by the memory unit
• Logical and physical addresses are the same in compile-time
and load-time address-binding schemes; logical (virtual) and
physical addresses differ in execution-time address-binding
scheme
• Logical address space is the set of all logical addresses
generated by a program
• Physical address space is the set of all physical addresses
generated by a program
Segmentation
• Memory-management scheme that supports user view of memory
• A program is a collection of segments
• A segment is a logical unit such as:
main program
procedure
function
method
object
local variables, global variables
common block
stack
symbol table
arrays
User’s View of a Program
Logical View of Segmentation

4
1

3 2
4

user space physical memory space

Segmentation Architecture
• Logical address consists of a two :
<segment-number, offset>,

• Segment table – maps two-dimensional physical addresses;

each table entry has:
• base – contains the starting physical address where the segments
reside in memory
• limit – specifies the length of the segment

• Segment-table base register (STBR) points to the segment

table’s location in memory

• Segment-table length register (STLR) indicates number of

segments used by a program;
segment number s is legal if s < STLR
Segmentation Architecture (Cont.)
• Protection
• With each entry in segment table associate:
• validation bit = 0  illegal segment
• read/write/execute privileges
• Protection bits associated with segments; code sharing
occurs at segment level
• Since segments vary in length, memory allocation is a
dynamic storage-allocation problem
• A segmentation example is shown in the following diagram
Segmentation Hardware
Paging
• Physical address space of a process can be noncontiguous;
process is allocated physical memory whenever the latter is
available
• Avoids external fragmentation
• Avoids problem of varying sized memory chunks
• Divide physical memory into fixed-sized blocks called frames
• Size is power of 2, between 512 bytes and 16 Mbytes
• Divide logical memory into blocks of same size called pages
• Keep track of all free frames
• To run a program of size N pages, need to find N free frames
and load program
• Set up a page table to translate logical to physical addresses
• Backing store likewise split into pages
• Still have Internal fragmentation
Address Translation Scheme
• Address generated by CPU is divided into:
• Page number (p) – used as an index into a page table which contains
base address of each page in physical memory
• Page offset (d) – combined with base address to define the physical
memory address that is sent to the memory unit
page number page offset
p d
m -n n
• For given logical address space 2m and page size 2n
Paging Hardware
Paging Model of Logical and Physical Memory
Paging Example

n=2 and m=4 32-byte memory and 4-byte pages

Free Frames

Before allocation After allocation

Implementation of Page Table
• Page table is kept in main memory
• Page-table base register (PTBR) points to the page table
• Page-table length register (PTLR) indicates size of the page
table
• In this scheme every data/instruction access requires two
memory accesses
• One for the page table and one for the data / instruction
• The two memory access problem can be solved by the use
of a special fast-lookup hardware cache called associative
memory or translation look-aside buffers (TLBs)
 Implementation of Page Table (Cont.)
• Some TLBs store address-space identifiers (ASIDs) in each
TLB entry – uniquely identifies each process to provide
address-space protection for that process
• Otherwise need to flush at every context switch
• TLBs typically small (64 to 1,024 entries)
• On a TLB miss, value is loaded into the TLB for faster access
next time
• Replacement policies must be considered
• Some entries can be wired down for permanent fast access
Memory Protection
• Memory protection implemented by associating protection
bit with each frame to indicate if read-only or read-write
access is allowed
• Can also add more bits to indicate page execute-only, and so on
• Valid-invalid bit attached to each entry in the page table:
• “valid” indicates that the associated page is in the process’ logical
address space, and is thus a legal page
• “invalid” indicates that the page is not in the process’ logical
address space
• Or use page-table length register (PTLR)
• Any violations result in a trap to the kernel
Valid (v) or Invalid (i) Bit In A Page
Table
Address-Translation Scheme
Three-level Paging Scheme
Logical to Physical Address Translation
End