Scribd
Upload
26 views

Lec 1 Part2 M1 Digital Design Flow

Uploaded by

Yasser Hanafy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
26 views

Lec 1 Part2 M1 Digital Design Flow

Uploaded by

Yasser Hanafy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 21

Digital Design Flow & EDA Tools

Lecture 1
Digital Design Flow (Terminologies)

• System Level specification, design, and verification


• High Level Synthesis
• Logic Level synthesis
• Design for testability
• Test pattern generation and fault simulation
• Timing analysis and closure
• Area, delay, and poser estimation and analysis
Digital Design Flow
Specification

• The utilization of appropriate abstractions in order


to increase comprehension about a system, and to
enhance the probability of a successful
implementation of functionality in a cost-effective
manner
• Model the behavior of the entire system using a
high-level language such as C, C++, or using
graphical "model-based" design tools
Design and Verification

• Design: is the process of concurrent design of the


Hardware and the Software of the system’s
components
• Verification: The process of proving the integrity of
the system design, operation, and compliance to
the system specification
Synthesis
• High Level Synthesis: It’s the automated design
process that takes an abstract behavioral
specification of a digital system and finds a register-
transfer level (RTL) structure that realizes the given
behavior.
• Logic Level Synthesis: it’s the process by which an
abstract specification of desired circuit behavior,
typically at register transfer level (RTL), is turned into
a design implementation in terms of logic gates
Design for Testability
• Techniques that add testability features to a
hardware product design.
• The added features make it easier to develop and
apply manufacturing tests to the designed
hardware.
• The purpose of manufacturing tests is to validate
that the product hardware contains no
manufacturing defects that could adversely affect
the product's correct functioning.
Test Pattern Generation
• Method/Technology used to find a test sequence
that, when applied to a digital circuit, enables
automatic test equipment to distinguish between
the correct circuit behavior and the faulty circuit
behavior caused by defects
• The effectiveness of TPG is measured by the number
of modeled defects, or fault models, detectable and
by the number of generated patterns
Timing Analysis and
Closure
• the process by which a logic design consisting of
primitive elements such as combinatorial logic gates
(and, or, not, nand, nor, etc.) and sequential logic
gates (flip flops, latches, memories) is modified to
meet its timing requirements
• The main steps of the design flow, which may be
involved in this process, are
• logic synthesis,
• placement,
• clock-tree synthesis
• routing
Y-chart
Y-Transformations
Design Steps
High- Functional
Specification
level
s
Descriptio Descriptio
n n

Behaviora Structura
l VHDL, l VHDL
C
Design Steps
High-level Functional
Specification
Descriptio
s
n Descriptio
n Synthesis
Physical
Technology
Placed DesignGate- Logic
&
Routed Mapping
level
Design
Descriptio
n
Design

X=(AB*CD)+
(A+D)+
(A(B+C))
Y = (A(B+C)
Packaging +AC+
Fabri D+A(BC+D))
-
cati
on
System Level Design
• Benefits of C++ for high level design
• Faster implementation of the specifications.
• The behavior of the system can be practiced in early
phase.
• Early discovery of errors in the specifications before the
manufacturing begins
• Early performance estimations are possible
• Find possible bottlenecks
• Easy design space exploration
Behavioral Domain
Behavioral Level
Example
Data[i]

i=0 i=7 * ∑

Weight[i]
Behavioral Level
Example
#include <ac_int.h>
#include <ac_array.h>
#include <ac_channel.h>
#pragma hls_design top
void da_intro (ac_channel<ac_array<uint10,8> > &data_in,
ac_channel<ac_array<uint10,8> >
&weight_in,
ac_channel<ac_array<uint23,1> > &data_out)
{
uint23 acc =0;
ac_array<uint10,8> data, weight;

data = data_in.read();
weight = weight_in.read();

for(int i=0; i<8; i++)


{ acc += data[i] * weight[i]; }

data_out.write(acc);
}
RTL Design and Test
RTL (1)
module unsig_altmult_accum
(
input [7:0] dataa,
input [7:0] datab,
input clk, aclr, clken, sload,
output reg [15:0] adder_out
);

// Declare registers and wires


reg [15:0] dataa_reg, datab_reg;
reg sload_reg;
reg [15:0] old_result;
wire [15:0] multa;

// Store the results of the operations on the current


data
assign multa = dataa_reg * datab_reg;

// Store the value of the accumulation (or clear it)


always @ (adder_out, sload_reg)
begin
if (sload_reg)
old_result <= 0;
else
old_result <= adder_out;
end
RTL (2)
// Clear or update data, as appropriate
always @ (posedge clk or posedge aclr)
begin
if (aclr)
begin
dataa_reg <= 0;
datab_reg <= 0;
sload_reg <= 0;
adder_out <= 0;
end

else if (clken)
begin
dataa_reg <= dataa;
datab_reg <= datab;
sload_reg <= sload;
adder_out <= old_result + multa;
end
end
endmodule
Universal Verification Methodology
• Class libraries needed for the development of well
constructed, reusable SystemVerilog based
Verification environment
• In simple words, UVM consists of a set of base
classes with methods defined in it, the
SystemVerilog verification environment can be
developed by extending these base classes.

You might also like