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 s sor
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, P
iram
a
iJ
la xm
ta
t GDigital Design & Computer Organization
e e
ha
Dr
. B
(BCS302) (3:0:2)

Text Books:
1. Digital Logic and Computer Design, M. Morris
Mano, Pearson Edu. 2016
2. Computer Organization: C Hamacher, Z Vranesic,
S Zaky:, Tata McGraw Hill, 5th Edition, 2011.
 s sor
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Module-1

Combinational Circuits
 SUM-of-PRODUCTS
es sor METHOD
rof
• The four possibleP
a m , ways to AND two input signals that are in
air
complemented
m i J and uncomplemented form.
lax
• These
eet outputs are called fundamental products.
a
G
h at
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• The fundamental products are also called minterms.

• Products A' B', A'B, AB', AB are represented by m0 , m1 , m2
and m3 respectively.
• The suffix i of mi comes from decimal equivalent of binary
values that makes corresponding product term high.
 o r
• ANDing two variables ofe
s s and their complements
P r
,
iram
i Ja
la xm
eta
t Ge
Bha
r.
D • ANDing three variables and their complements
 sor
Sum-of-ProductsroEquation fes
, P
• To get the iramsum-of-products solution for a given a
i Ja
truth a la xtable,
m locate each output 1 in the truth table
e et
aand
t G write down the fundamental product.
. Bh
Dr

Y =A B C+ A B C+ AB C + ABC

Alternate representation of Table

Y = F(A, B, C) =  m (3, 5, 6, 7) also known as Cannonical sum form

 TRUTH TABLE TO KARNAUGH
sso
r MAP (K-map)- Two variable
rofe
P
• A Karnaugh ira m , map is a visual display of the
Ja
fundamental
a x m i products needed for a sum-of-products
tal
solution.
t Ge
e
ha
Dr • Convert the Truth table in to K-map
. B
 o r
• Three-VariableofMaps-1 es s Type
P r
,
iram
i Ja
la xm
eta
t Ge
Bha
D r.
 s sor
Three-Variable Maps-2 fe Type
o
, Pr
iram
i Ja
la xm
eta
t Ge
Bha
.
Dr

0 1 3 2

4 5 7 6
 sor
EXAMPLE 3-1:ProDraw fes
k-map for the following:
m ,
a
• F = x’yzi Ja+ir x’yz’ + xy’z’ + xy’z
la xm
Ans Ge
etareference =(3,2,4,5)
t
ha
D r. •
B

0 1 3 2
1 1
4 5 7 6
1 1
 • Four-Variable Maps
s sor
e of
P r
,
iram
a
m iJ
a lax
G eet
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 PAIRS, QUADS, AND
es soOCTETS
r
rof
, P
• Pairs a iram y= ABC
m iJ
a lax
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 s sor
rofe
• Whenever P
a m , we see a pair of horizontally or
air
vertically x mi
J adjacent 1s, we can eliminate the
a la
variable
t G e et
that appears in both complemented
ha
Dr
. B and uncomplemented form.

• The remaining variables (or their

complements) will be the only ones appearing
in the single-product term corresponding to
the pair of 1s.
 s sor
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Y= A C D Y= A C D

Y= A B’ C’
Y= AC’D’ +A’BD
 The Quad s sor
rofe
P
,
a m
• A quad Jair is a group of four 1s that are
x mi
la
horizontally
e eta or vertically adjacent.
a tG
h
D r. B
• The 1s may be end-to-end or in the form of a
square.
• When you see a quad, always encircle it
because it leads to a simpler product.
• A quad eliminates two variables and their
complements.
 s sor
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Y= AB Y=AC
 sor
The Octet P rofe
s
m ,
a
• The octet Jair is a group of eight 1 s
x mi
la
• An e e octet like this eliminates three variables
ta
a tG
. B and their complements.
h
D r

Y= A
 KARNAUGH SIMPLFICATIONS
ofe
s sor
P r
m ,
ira
• As youmiknow,
Ja a pair eliminates one variable and its
lax
complement,
e eta a quad eliminates two variables and
tG
h their complements, and an octet eliminates three
a
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D
variables and their complements.

• Because of this, after you draw a Karnaugh map,

encircle the octets first, the quads second, and the
pairs last.

• In this way, the greatest simplification results.

 s sor
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Y=AC’ + A’B’D + CD’

 Overlapping Groups
fes sor
P ro
,
• It is allowed toiuseram the same 1 more than once.
• Always overlap i Ja groups if possible. That is, use the 1s more than once to get the
la xm
largestta groups you can.
e e
t G
Bha
.
Dr

Y= A + A’BC’D
Y= A + BC’D It is valid to encircle the 1’s as shown in
above figure but then the isolated 1
OPTIMAL results in a more complicated
equation:
 Rolling the Map
ofe
s sor
P r
m ,
a ira
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Y= BC’D’ + BCD’ Y= BD’

OPTIMAL
SIMPLIFICATION
= BD’(C’+C)
= BD’
 s sor
fe
• Visualize mpicking ,P
ro
up the Karnaugh map and
ira
rolling xm
i it
J so that the left side touches the right
a
la
side.
Ge
eta
t
Bha
D r.

• If you are visualizing correctly, you will realize

the two pairs actually form a quad.

• To indicate this, draw half circles around each

pair,
 More Examplesfessor
P ro
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iram
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OPTIMAL
 s sor
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OPTIMAL
 s sor
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iram
a
m iJ
ax
• Ans: e eta l
a tG
h
D r. B
 s sor
• Simplify F=, rofe
P
iram
a
m iJ
a lax
G eet
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 s sor
rofe
, P
iram
a
m iJ
a lax
eet
a tG
h
.B
D Ans:
r yz +xz’
 s sor
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iram
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 sor
• EXAMPLE 3-5: P rofe Simplify the Boolean function;
s
,
am
F(w, x,y, i Ja z) = ∑(0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14)
ir
la xm
eta
t Ge
Bha
D r.
 s sor
rofe
P ,
m
• EXAMPLE Jair 3-4: Simplify the Boolean
a function:
x mi
e etaF(x,y,
la z) = ∑(0, 2, 4, 5, 6)
a tG
r. B Ans:
h
D
 Eliminating Redundant
s sor Groups
o fe
P r
m ,
• After you Ja irahave finished encircling groups, eliminate
m i
anytaredundant
lax group.
e e
tG
• haThis is a group whose 1s are already used by other
. B
Dr groups.
 Eliminating an unnecessary s sor group
rofe
• Ans: Y= A’BC’ m , P +A’CD+AC’D +ABC
a
air
• xm
i J
ta la
G ee
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 Conclusion s sor
rofe
P
Here is a summary a m , of the Karnaugh-map method for simplifying
a ir
Boolean equations:
mi
J
la x
ta
ee
1. aEnter
tG a 1 on the Karnaugh map for each fundamental product
r Bh produces a I output in the truth table. Enter 0s elsewhere.
. that
D

2. Encircle the octets, quads, and pairs. Remember to roll and

overlap to get the largest groups possible.

3. If any isolated 1s remain, encircle each.

4. Eliminate any redundant group.

5.Write the Boolean equation by ORing the products

corresponding to the encircled groups.
 What is the simplified s sor Boolean equation for the
rofe
following logic
am
, equation
P expressed by minterms?
Jair
i
xm
Y=F(A,B,C,D)=
eta la  m(7,9, 10, 11, 12, 13, 14, 15)
t Ge
Bha
D r.

Y=AB+AC+AD+BCD
No redundant group
 o r
Simplify the following ofe
s s Boolean function using K-map.
P r
,
iram
i Ja
la xm
eta
t Ge
a
. Bh
Dr
 DON'T-CARE CONDITIONS
es sor
rof
P ,
m
• In someJairdigital systems, certain input conditions
a
mi
never ta la occur during normal operation; therefore, the
x
e e
h acorresponding
tG output never appears.
D r. B
• Since the output never appears, it is indicated by an
X in the truth table.

• The X is called a don't-care condition.

• Whenever you see an X in a truth table, you can let it

equal either O or 1, whichever produces a simpler
logic circuit.
 s sor
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Boolean equation is
Y = AD
 s sor
e
ofideas
Remember these , P r about don't-care conditions:
iram
i Ja
la xm
1. Given
e eta the truth table, draw a Karnaugh map with
tG
h 0s, 1s, and don't-cares.
a
D r. B

2. Encircle the actual 1s on the Karnaugh map in the

largest groups you can find by treating the don't cares
as 1s.

3. After the actual 1s have been included in groups,

disregard the remaining don't cares by visualizing them
as 0s.
 • Suppose Table fe3.8 r
sso has high output for an input of
ro
0000, low aoutput, m , P for 0001 to 1001, and don't cares
ir
for 1010 m i to 1111. What is the simplest logic circuit
Ja
lax
with
eet this truth table?
a
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Y=A’B’C’D’
 • Give the simplest s sor logic circuit for following logic
rofe
equation where am
, P d represents don't-care condition for
ir
following i Ja locations.
la xm
a
Ge
et F(A, B, C, D) = m(7) + d(10, 11, 12, 13, 14, 15)
t
Bha
.
Dr
Boolean equation is:
Y=BCD
 s sor
rofe
P
Simplify the air
a m , following Boolean function using
J
ala
x mi K-map
e et
t G
Bha
.
Dr
Y=f(a,b,c,d)=m(6,7,9,10,13)+d(1,4,5,11,15)

Ans: f(a,b,c)=a’b + ab’c + c’d

Or
f(a,b,c)=a’b + ab’c + ad
 s sor
rofe
P
Simplify the air
a m , following Boolean function using
J
ala
x mi K-map
e et
t G
Bha
.
Dr
 s sor
rofe
P
Simplify the air
a m , following Boolean function using
J
ala
x mi K-map
e et
t G
Bha
.
Dr
 EXAMPLE 3-12: Simplify s sor the Boolean function:
rofe
F(w, x, y, z and the , Pdon’t-care conditions:
iram
i Jd(w,
a x, y, z) = Σ(0, 2, 5)) = Σ(1,3, 7, 11, 15)
la xm
Ans : e1)etaIn sum-of-products function 11) In POS form
aFt G= w′ z + y z
. Bh
Dr
 PRODUCT-OF-SUMS
fes sor METHOD
P ro
,
• This method iram is similar to sum-of-products.
i Ja
• Given la xma truth table, you identify the fundamental
eta
t Ge
sums needed for a logic design.
h a
r.B
D • Then by ANDing these sums, you get the product-of-
sums equation corresponding to the truth table.
• Differences between the two approaches:
With the sum-of-products method, the
fundamental product produces an output 1 for the
corresponding input condition.
But with the product-of-sums method, the
fundamental sum produces an output 0 for the
corresponding input condition.
 Converting a TruthesTable
sor to an Equation
rof
, P
iram
a
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1. The variable is uncomplemented when the corresponding

input variable is 0.
2. To get the product-of-sums equation, all you have to do is
AND the fundamental sums:

This is the product-of-sums equation for Table 3.9.

 s sor
ro fe
Simplify the following, PBoolean function using K-map in POS
Ans F’= A’C’+A’B+BC’ r m SOP form
aIN
i
Complementing again,i JaIn POS form shown below
la xm
eta
t Ge
a
. Bh
Dr
 EXAMPLE 3-12: Simplify s sor the Boolean function:
rofe
F(w, x, y, z) and the , P don’t-care conditions:
iram
i Jd(w,
a x, y, z) = Σ(0, 2, 5)) = Σ(1,3, 7, 11, 15)
la xm
Ans : e1)etaIn sum-of-products function
aFt G= w′ z + y z
. Bh
Dr
 EXAMPLE 3-12: Simplify s sor the Boolean function:
rofe
F(w, x, y, z) and the , P don’t-care conditions:
iram
i Jd(w,
a x, y, z) = Σ(0, 2, 5)) = Σ(1,3, 7, 11, 15)
la xm
Ans : e11)
eta In POS form: The complement function is simplified to:
tG
Bh ′ = z′ + w y ′
aF
.
Dr • Complementing again, we obtain a simplified product of sums
function:
• F = z (w′ + y)
 s sor
• In POS eachProsum fe term is called maxterm and is
m ,
designated Jair by Mi
a
x mi
ta la
e e
tG
• h Equation Y =(A+ B + C)(A + B’ + C’)(A’ + B‘+ C)in terms
a
D r. B
of maxterm can be represented as
Y = F(A, B, C) = M(0, 3, 6)

• where ‘' symbolizes product, i.e. AND operation.

This kind of representation of a truth table is also
known as canonical product form.
 Logic Circuit s sor
rofe
P
• After youirhave am
, a product-of-sums equation, you can
Ja
get the a x m logic circuit by drawing an OR-AND network,
i
tal
or
tG
e if you prefer, a NOR-NOR network.
e
Bha
.
Dr
• In below equation each sum represents the output
of a 3-input OR gate.

• Furthermore, the logical product Y is the output of a

3-input AND gate.

• Therefore, you can draw the logic circuit as shown

below:
 or
• fAess3-input OR gate is not available as a TTL
P ro chip. So, the circuit is not practical.
m ,
a
Jair • With De Morgan's first theorem, however,
x mi
ta la you can replace the OR-AND circuit by the
e e
at
G NOR-NOR circuit.
h
r.B
D
 Conversion betweensoSOP
r and POS
fes
ro
• We have seen , P that SOP representation is obtained by
iram
considering i Ja ones in a truth table while POS comes
a xm
considering
eta l zeros.
t Ge
•BhaIn SOP, each one at output gives one AND term which is
.
Dr finally ORed.
• In POS, each zero gives one OR term which is finally
ANDed.
• Thus SOP and POS occupy complementary locations in a
truth table and one representation can be obtained from
the other by
(i) identifying complementary locations,
(ii) changing minterm to maxterm or reverse, and finally
(iii) changing summation by product or reverse.
 s sor
• Y = F(A, B, C) , P r fe
o= 
M(0, 3, 6) = m(1, 2, 4, 5, 7)
iram
i Ja
la xm
a
Similarly
a t Ge
et
Table 3.4 can be represented as
Bh
Dr
.
Y = F(A, B, C) = m (3, 5, 6, 7) = M (0, 1, 2, 4)

• This is also known as conversion between

canonical forms.
 sor
• Give simplest POS rofe form of
s Karnaugh map shown
, P
below byaigrouping ram zeros.
i J
• In SOP= a la xm
e et
Y’=
ha
t GA’B’+A’C’+A’D
r. B
D • In POS ,complement and
Ans is :
 • Give simplest POS s r
oform of Karnaugh map shown
fes
ro
below by grouping
am
, P zeros.
Jair
i
la xm
ta
• In t Ga
e Karnaugh
e map if don't
Bha
D care conditions exist, we may
r.

consider them as zeros if that

gives larger group size.
This in turn reduces number of Y’= C’+B’D’ in SOP
literals in the sum term. IN POS-
 s sor
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Combinational Logic
 or
rofe
s s Adders
• Digital computers
P
m , perform a variety of information-
ira
processing i J tasks.
a
a xm
• This et l
a simple addition consists of four possible elementary
e
Goperations,
h a t namely, 0 + 0 = 0, 0 + 1 = 1, 1 + 0 = 1, -Gives
r.B sum and 1 + 1 = 10- This gives carry and sum.
D
• A combinational circuit that performs the addition of two
bits is called a half-adder.
• One that performs the addition of three bits (two significant
bits and a previous carry) is a full-adder.
 s r
oHalf-Adder
s
rofe
• This circuitm, needs two binary inputs and two binary
P
ira
outputs.
iJ
a
m
a lax
G eet
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• The simplified Boolean functions for the two outputs can

be obtained directly from the truth table. The simplified
sum of products expressions are:
• S = x′y + xy′
• C = xy
 s r
oHalf-Adder
s
rofe
• Various Implementations
am
, are: P
Jair
m i
a lax
G eet
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 r
e Half--Adder
s so
o f
Pr
• Various Implementations , are:
a m
Jair
• Simplification
a x mi of Simplification of
etal
S=
a t Gexx’+ xy’+x’y+ yy’ C= (x’+y’)’=(x’)’ (y’)’= xy
h
r.B = xy’+x’y
D
 s r
oFull-Adder
s
rofe
• It consistsamof
, three inputs and two outputs.
P
Jair
m i
a lax
Geet
Truth table of Full Adder
at
h
r.B
D
 Full-Adder
sor
s
• Maps for full-adder rofe
, P
iram
i Ja
la xm
eta
t Ge
Bha
.
Dr
 Full-Adder
sor
s
• Implementation rofe of full-adder in sum of products
, P
iram
i Ja
la xm
eta
t Ge
Bha
.
Dr
 Full-Adder
sor
s
• Implementation rofe of full-adder with two half-adders
, P
m
and anJaOR ira gate
x mi
ta la
e e
a tG
h
r.B
D
 Referance sor
es
Simplification Pof rof -
m ,
• z(xy’+x’y)’= a
i Jair z((xy’)’ (x’y)’)= z((x’+y)(x+y’))
a xm
= z(x’x+x’y’+xy+yy’)=z(xy+x’y’)
eta l
t Ge
a
. Bh
Dr

Note: half adder and full adder NAND

implementation has to be done in Lab
 Subtractors
sor
Half-Subtractor rofes
, P
• A half-subtractoriram is a combinational circuit that subtracts
Ja
two abits i
l xm and produces their difference.
eta
• GIte also has an output to specify if a 1 has been borrowed.
h at
r.B Designate the minuend bit by x and the subtrahend bit by y.
D
To perform x - y, we have to check the relative magnitudes
of x and y.
• If x > y, we have three possibilities: 0 - 0 = 0, 1 - 0 = 1, and
1 - 1 = 0. The result is called the difference bit.
• If x < y, we have 0 - 1, and it is necessary to borrow a 1
from the next higher stage. The 1 borrowed from the next
higher stage adds 2 to the minuend bit
 Subtractors
sor
Half-Subtractor rofes
, P
am for the input-output relationships of a half-
• The truthirtable
i Ja
subtractor
ax
m can now be derived as follows:
etal
G e
h at
r.B
D

0 1 0 1 (5)
- 1 0 1 0 (10)
1
-------------------
1 1 0 1 1 (-5 in 2’s complement)
borrow
 Subtractors
sor
Full-Subtractor rofes
, P
• The three iram inputs, x, y, and z, denote the minuend,
i Ja
subtrahend,
a xm and previous borrow, respectively. The two
ta l
G
outputs,
e e D and B, represent the difference and output
h at borrow, respectively. The truth table for the circuit is as
r.B
D follows:
 Subtractors
sor
Full-Subtractor rofes
P ,
iram
a
m iJ
a lax
G eet
h at
r.B
D

Note- XOr implementation and NAND

implementation of half and full
subtractor has to b done in lab
 Binary
so r Parallel Adder
• Two binary numbers es
P ro of n bits each can be added by means of this
f
circuit. m ,
a
Jair
• To demonstrate x mi with a specific example, consider two binary
a la
numbers,
e et A = 1011 and B = 0011, whose sum is S = 1110.
t G
h a
•. B When a pair of bits are added through a full-adder, the circuit
D r
produces a carry to be used with the pair of bits one significant
position higher.
 Binary
so r Parallel Adder
• A. binary parallelrofadder es is a digital function that produces the
P
,of two binary numbers in parallel. It consists of
arithmetic sum a m
Jair
full-adders x mi connected in cascade.
ta la
• witheethe output carry from one full-adder connected
a tG
Bhthe input carry of the next full-adder.
r.to
D 0 1 0 0 1 1 1 1

Ai Bi Ci Ci+1 Si
0
0 1
1 0

1 1 1
0
 Binary
so r Parallel Adder
• Figure 5-1 showsrofethe s
interconnection of four full-adder (FA)
P
, a 4-bit binary parallel adder.
circuits to provide a m
Jair
• The augend x mi bits of A and the addend bits of B are designated by
ta la
subscript
G e e numbers from right to left, with subscript 1 denoting the
h at
low-order bit.
r.B
D
• The carries are connected in a chain through the full-adders. The
input carry to the adder is C1 and the output carry is C5.
• The S outputs generate the required sum bits.
• When the 4-bit full-adder circuit is enclosed within an IC
package, it has four terminals for the augend bits, four terminals
for the addend bits, four terminals for the sum bits, and two
terminals for the input and output carries.
 Binary
or
Parallel Adder
es s
• BCD to Excess-3 code ro converter using logic gates
f
P
• Binary CodedraDecimal m, (BCD) Code -​ Digital numbers are represented,
i
i Ja
stored and transmitted as group of binary bits. This group is also called as
m
lax decimals. Weighted binary codes are those binary codes which
binarytacode
e e
obey
t G the positional weight principle. Each position of the number represents a
h a
r. B specific weight. Several systems of the codes are used to express the decimal
D digits 0 through 9. In these codes each decimal digit is represented by a group
of four bits.
• In this code each decimal digit is represented by a 4-bit binary number. BCD is
a way to express each of the decimal digits with a binary code. In the BCD,
with four bits we can represent sixteen numbers (0000 to 1111). But in BCD
code only first ten of these are used (0000 to 1001). The remaining six code
combinations i.e. 1010 to 1111 are invalid in BCD.
 Binary
so r Parallel Adder
• BCD to Excess-3rcode es
o f converter using logic gates
, P
• Excess-3 Code m
a ir - The Excess-3 code is also called as XS-3 code.
a
i J
It is non-weighted
a xm code used to express decimal numbers. The
ta l
Excess-3
G e e code words are derived from the 8421 BCD code words
h at
adding (0011)2 or (3)10 to each code word in 8421. The excess-3
r.B
D codes are obtained as follows -
 Binary
so r Parallel Adder
• BCD to Excess-3 code es
P ro converter using logic gates
f
m ,
• BCD to Excess-3 ira Code Converter - Excess-3 binary code is an
Ja
unweighted i
la xm self-complementary BCD code. Self-Complementary
property
eta means that the 1’s complement of an excess-3 number is
t Ge
a excess-3 code of the 9’s complement of the corresponding
hthe
. B
Dr decimal number. This property is useful since a decimal number
can be nines’ complemented (for subtraction) as easily as a binary
number can be ones’ complemented; just by inverting all bits.
• BCD digit can be converted to it’s corresponding Excess-3 code
by simply adding 3 to it.
 Binary
so r Parallel Adder
fes
P ro
m ,
a ira
m iJ
a lax
G eet
h at
r.B
D
 Binary
so r Parallel Adder
fes
• BCD to Excess-3 ro
,P
iram
a
m iJ
a lax
G eet
h at
r.B
D
 Binary
so r Parallel Adder
• The application of thisofMSI es function to the design of a combinational circuit is
r
Pfollowing
demonstrated in the m , example.
a
ir a 4-bit full-adders is the TTL type 74283 IC.
• *An example Jaof
x mi
ta la
e e
a tG
h
D r. B
 Binary
so r Parallel Adder
• The application of thisofMSI es function to the design of a combinational circuit is
r
Pfollowing
demonstrated in the m , example.
a
Jair
x mi
ta la
e e A4A3A2A1 0101=(5) BCD input
a tG B4B3B2B 1 + 0011= add factor
Bh
D r. Ex-3 code= 1000
Ci=0
 Binary
so r Parallel Adder
fes
• BCD to Excess-3 ro
,P
iram
a
m iJ
a lax
G eet
h at
r.B
D
 B3B2B1B 0 0101=(5)
s sor add factor + 0011= (3)
e
• Lab experiment rof
, P - BCD to Excess-3 Ex-3 code= 1000
iram
a
m iJ
a lax
G eet
h at
r.B
D
 s sor
ro fe
• Lab experiment- , P BCD to Excess-3
iram
i Ja
la xm
eta
t Ge
Bha
D r.
 B3B2B1B 0 0101=(5)
s sor add factor + 0011= (3)
e
• Lab experiment rof
, P -BCD to Excess-3 Ex-3 code= 1000
iram
a
m iJ
a lax
G eet
h at
r.B
D
 Carry
so r Propagation
fes
• ro
As in any combinational P circuit, the signal must propagate through the
m ,
gates beforeJathe ira correct output sum is available in the output terminals.
i
mpropagation
• The total la x time is equal to the propagation delay of a typical
a
ettimes the number of gate levels in the circuit. The longest
gate e
a tG
h
r. B propagation delay time in a parallel adder is the time it takes the
D carry to propagate through the full-adders
• Since each bit of the sum output depends on the value of the input carry,
the value of Si in any given stage in the adder will be in its steady-state
final value only after the input carry to that stage has been propagated.
• Consider output S4 in Fig. 5-1. Inputs A4 and B4 reach a steady
value as soon as input signals are applied to the adder. But input
carry C4 does not settle to its final steady-state value until C3 is
available in its steady-state value.
• Similarly C3 has to wait for C2, and so on down to C1. Thus only
after the carry propagates through all stages will the last output S4
and carry C5 settle to their final steady-state value.
 Carry
r Propagation
s so
rofe
, P
iram
a
m iJ
a lax
G eet
h at
r.B
D

• The number of gate levels for the carry propagation can be found
from the circuit of the full-adder.
 Carry
or
Propagation
es s
• The signals at Pi and ro Gi settle to their steady-state value after the
f
, P
propagation ithrough
ra m their respective gates.
i Ja
• These two xm signals are common to all full-adders and depend only
la
a input augend and addend bits.
onGthe
e et
a t
•r. BhThe signal from the input carry, Ci, to the output carry, Ci+1,
D
propagates through an AND gate and an OR gate, which
constitute two gate levels.
• If there are four full-adders in the parallel adder, the output
carry C5 would have 2 × 4 = 8 gate levels from C1 to C5.
• The total propagation time in the adder would be the propagation
time in one half-adder plus eight gate levels.
• For an n-bit parallel adder, there are 2n gate levels for the carry to
propagate through.
 Carry
r Propagation
s so
• There are several techniques
ofe for reducing the carry propagation time in a
r
P widely used technique employs the principle of look-
parallel adder. Them,most
a
ahead carry. Jair
x mi
ta la
e e
a tG
h
D r. B
 Carry
r Propagation
s so
• write the Boolean function ofe for the carry output of each stage and substitute for
r
P the previous equations:
each Ci its value from ,
iram
i Ja Note: C1 is initial carry
m
a lax
e et
a tG
h
D r. B

• Note -that C4 does not have to wait for C3 and C2 to propagate; in fact,
C4 is propagated at the same time as C2 and C3.
• A typical look-ahead carry generator is the IC type 74182. It is implemented
with AND-OR-INVERT gates. It also has two outputs, G and P, to generate C5
= G + PC1.
 Carry
r Propagation
s so
rofe
, P
iram
a
m iJ
a lax
G eet
h at
r.B
D
 Carry
r Propagation
s so
e
The construction of a 4-bitPparallel rof adder
,
with a look-ahead carry iramscheme is shown
iin Fig. 5-5. i Ja
la xm
eta
t Ge
Bha
.
Dr
 Carry r Propagation
s so
• The output of the rfirsto fe exclusive-ORgate generate the Pi variable,
P
and the ANDiragalem, generates the Gi variable.
i Ja
• All thexP’s m and G’s are generated in two gate levels. The carries
la
eta
areGepropagated through the look-ahead carry generator (similar to
h at in Fig. 5-4) and applied as inputs to the second exclusive-OR
that
r.B
D gate. After the P and G signals settle into their steady-state values,
all output carries are generated after a delay of two levels of
gates.
• Thus, outputs S2 through S4 have equal propagation delay times.
(as c2 ,c3 and c4 not depends on each other, only on c1)