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Lecutre-8 Cache Memory

Lecutre-8 Cache Memory

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7 views

Lecutre-8 Cache Memory

Lecutre-8 Cache Memory

Uploaded by

ahmed15-4426
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Lecture-8

Chapter - 4
Computer Organization and Architecture Designing -
William Stallings

Cache Memory

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Memory Hierarchy

• Registers
– In CPU
• Internal or Main memory
– May include one or more levels of cache
– “RAM”
• External memory
– Backing store

Fig: Memory Hierarchy Diagram

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Performance

• Access time
– Time between presenting the address and getting the valid data
• Memory Cycle time
– Time may be required for the memory to “recover” before next access
– Cycle time is access + recovery
• Transfer Rate
– Rate at which data can be moved

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Hierarchy List

• Registers
• L1 Cache
• L2 Cache
• Main memory
• Disk cache
• Disk
• Optical
• Tape

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Cache and Main Memory

• Small amount of fast memory


• Sits between normal main memory and CPU
• May be located on CPU chip or module

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Cache/Main Memory Structure

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Cache operation – overview

• CPU requests contents of memory location


• Check cache for this data
• If present, get from cache (fast)
• If not present, read required block from main memory to cache
• Then deliver from cache to CPU
• Cache includes tags to identify which block of main memory is in each cache slot

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Cache Read Operation - Flowchart

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Cache Addressing

• Where does cache sit?


– Between processor and virtual memory management unit
– Between MMU and main memory
• Logical cache (virtual cache) stores data using virtual addresses
– Processor accesses cache directly, not thorough physical cache
– Cache access faster, before MMU address translation
– Virtual addresses use same address space for different applications
• Must flush cache on each context switch
• Physical cache stores data using main memory physical addresses

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Mapping Function

• The cache can hold 64 Kbyte


• Data can be transferred between main memory and the cache in block of 4 bytes each
– i.e. cache is 16k = 214 lines of 4 bytes each
• Main memory consists of 16Mbytes, 24 bit address directly addressable 224 = 16M
--i.e. 4M blocks of 4 bytes each

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Direct Mapping

• Each block of main memory maps to only one cache line


– i.e. if a block is in cache, it must be in one specific place
• Address is in two parts
• Least Significant w bits identify unique word
• Most Significant s bits specify one memory block
• The MSBs are split into a cache line field r and a tag of s-r (most significant)

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Direct Mapping Address Structure

• 24 bit address
• 2 bit word identifier (4 byte block)
• 22 bit block identifier
– 8 bit tag (=22-14)
– 14 bit slot or line
• No two blocks in the same line have the same Tag field
• Check contents of cache by finding line and checking Tag

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Direct Mapping from Cache to Main Memory

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Direct Mapping Summary

• Address length = (s + w) bits


• Number of addressable units = 2s+w words or bytes
• Block size = line size = 2w words or bytes
• Number of blocks in main memory
= 2s+ w/2w = 2s
• Number of lines in cache = m = 2r
• Size of tag = (s – r) bits

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Direct Mapping pros & cons

• Simple
• Inexpensive
• Fixed location for given block
– If a program accesses 2 blocks that map to the same line repeatedly, cache misses are very
high

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Associative Mapping

• A main memory block can load into any line of cache


• Memory address is interpreted as tag and word
• Tag uniquely identifies block of memory
• Every line’s tag is examined for a match
• Cache searching gets expensive

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Associative Mapping Address Structure

Tag Word
22 bits 2 bits

• 22 bit tag stored with each 32 bit block of data


• Compare tag field with tag entry in cache to check for hit
• Least significant 2 bits of address identify which 16 bit word is required from 32 bit
data block
• e.g.
– Address Tag Data Cache line
– FFFFFC FFFFFC 24682468 3FFF

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Associative Mapping from Cache to Main Memory

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Associative Mapping Summary

• Address length = (s + w) bits


• Number of addressable units = 2s+w words or bytes
• Block size = line size = 2w words or bytes
• Number of blocks in main memory
= 2s+ w/2w = 2s
• Number of lines in cache = undetermined
• Size of tag = s bits

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Set Associative Mapping

• Cache is divided into a number of sets


• Each set contains a number of lines
• A given block maps to any line in a given set
– e.g. Block B can be in any line of set i
• e.g. 2 lines per set
– 2 way associative mapping
– A given block can be in one of 2 lines in only one set

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Set Associative Mapping Address Structure

Word
Tag 9 bit Set 13 bit 2 bit

• Use set field to determine cache set to look in


• Compare tag field to see if we have a hit
• e.g
– Address Tag Data Set number
– 1FF 7FFC 1FF 12345678 1FFF
– 001 7FFC 001 11223344 1FFF

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Mapping From Main Memory to Cache: v Associative

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Mapping From Main Memory to Cache: k-way Associative

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Set Associative Mapping Summary

• Address length = (s + w) bits


• Number of addressable units = 2s+w words or bytes
• Block size = line size = 2w words or bytes
• Number of blocks in main memory = 2d
• Number of lines in set = k
• Number of sets = v = 2d
• Number of lines in cache = kv = k * 2d
• Size of tag = (s – d) bits

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That’s All
Thank You

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