18ECC203J – Module 1

Intel 8086 – Architecture, Signals and Features

S–3

Prepared by,
Dr. R. Manohari
Dr.T.Rajalakshmi
 S–3
Architecture of 8086
 Microprocessor

3 Functional blocks
Computational Unit;
performs arithmetic and
Various conditions of the
results are stored as
Internal storage of data
status bits called flags in
logic operations
flag register

Register array or Data Bus

internal memory
ALU
Generates the
address of the
Instruction
Flag instructions to be
decoding unit
Register fetched from the
memory and send
through address
bus to the
Timing and memory
control unit PC/ IP

Control Bus Address Bus

Generates control signals for

internal and external Decodes instructions; sends
operations of the information to the timing and
microprocessor control unit
Architecture of 8086
8086 Internal Architecture

 The complete architecture is divided into two parts:

1. Bus Interface Unit
2. Execution Unit
8086 Internal Architecture

 BIU: It sends out addresses, fetches instructions from

memory, reads data from ports and memory and
writes data to ports and memory.
 EU: It tells the BIU where to fetch instructions or data
from, decodes instructions and executes instructions
Bus Interface Unit

 BIU contains
1. Instruction Byte Queue (6 bytes long)
2. Segment Registers
3. Instruction Pointer
4. Circuit for physical address calculations
Segment Registers (S – 2)

 Four Segment registers in the BIU are used to hold

the upper 16 bits of the starting addresses of
four memory segments that the 8086 is working with
at a particular time
Segment Registers (S – 2)

 Unlike 8085, the

8086 addresses
a segmented
memory
 A segment
register points to
the starting
address of a
memory
segment.
 Segment Registers (S – 2)

 Code Segment Register: Used to hold the upper 16 bits of

the starting address of code segment from which the BIU is
currently fetching instruction code bytes
 Data Segment Register & Extra Segment Register: Used
to hold the upper 16 bits of the starting addresses of data
segment and extra segment that are used for data
 Stack Segment Register: Used to hold the upper 16 bits of
the starting addresses of stack segment which is used to store
stack data
The Queue Operation
 Queue Operation cont…
 The 8086 has a 6-byte instruction prefetch queue.
 Thus even the largest (6-byte) instruction can be prefetched from the memory
and stored in the prefetched queue.
 This results in a faster execution of the instruction.
 In the beginning, the CS:IP is loaded with the required address from which the
execution is to be started.
 Initially, the queue will be empty and the microprocessor starts a fetch operation
to bring one byte (the first byte) of instruction code, if the CS:IP address is odd or
two bytes at a time, if the CS:IP address is even.
 When the first byte from queue goes for decoding and interpretation, one byte in
the queue becomes empty and subsequently the queue is updated.
 The microprocessor does not perform the next fetch operation till at least two
bytes of the instruction queue are emptied.
 Queue Operation cont…

 The queue is updated after every byte is read from the queue but the fetch
cycle is initiated by BIU only if at least two bytes of the queue are empty
and the EU may be concurrently executing the fetched instructions.
 The next byte after the instruction is completed is again the first opcode
byte of the next instruction.
 A similar procedure is repeated till the complete execution of the program.
 The fetch operation of the next instruction is overlapped with the execution
of the current instruction.
 While the execution unit is busy in executing an instruction, after it is
completely decoded, the bus interface unit may be fetching the bytes of the
next instruction from memory, depending upon the queue ststus.
Execution Unit
 It contains:
1. Control Circuitry
2. Instruction Decoder
3. Arithmetic Logic Unit (ALU)
4. Flag Register
5. General Purpose Registers
6. Pointers and Index Registers
Control Circuitry, Instruction Decoder,
ALU
 Control Circuitry in the EU directs the internal
operations
 A Instruction decoder translates instructions
fetched from memory into a series of actions which
the EU carries out
 16 bit arithmetic logic unit can add, subtract, AND,
OR, XOR, increment, decrement, complement or shift
binary numbers
Register Organization of 8086
Flag Register (S – 2)

 A flag is a flip-flop that indicates some condition

produced by the execution of an instruction or
controls certain operations of the EU
 A 16-bit flag register in the EU contains nine active
flags in the flag register
Flag Register (S – 2)
 8086 has 9 flags and they are divided into two
categories:
 Condition Flags
 Control Flags
 Condition Flags (S – 2)
 Condition flags represent result of last arithmetic or logical
instruction executed. Conditional flags are as follows:

 Carry Flag (CF): This flag is set if there is a carry /

borrow after an integer arithmetic.

 Auxiliary Carry Flag (AF): If an operation performed in

ALU generates a carry / borrow from lower nibble (i.e. D0 –
D3) to upper nibble (i.e. D4 – D7), then AF is set. It is used
in BCD Addition.

 Parity Flag (PF): This flag is used to indicate the parity

of result. If the result contains even number of 1’s, the
Parity Flag is set and for odd number of 1’s, the Parity Flag
Condition Flags (S – 2)

 Zero Flag (ZF): It is set; if the result of arithmetic or

logical operation is zero else it is reset.
 Sign Flag (SF): In sign magnitude format, the sign of
number is indicated by MSB bit. If the result of operation
is negative, sign flag is set.
 Overflow Flag (OF): It occurs when signed numbers are
added or subtracted. An OF indicates that the result has
exceeded the capacity of machine that is result is out of
range
Control Flags (S – 2)

 Control flags are set or reset deliberately to control

the operations of the execution unit. Control flags are
as follows:
 Trap Flag (TP):
 It is used for single stepping through a program
 It allows user to execute one instruction of a
program at a time for debugging.
 When trap flag is set, program can be run in single
step mode.
Control Flags (S – 2)

 Interrupt Flag (IF):

 It is an interrupt enable / disable flag.
 If it is set, the INTR interrupt of 8086 is enabled and
if it is reset then INTR is disabled.
Control Flags (S – 2)

 Directional Flag (DF):

 It is used with string operations.
 If it is set, string bytes are accessed from higher
memory address to lower memory address.
 When it is reset, the string bytes are accessed from
lower memory address to higher memory address.
 General Purpose Registers (S – 2)
 EU has eight general purpose registers,
labeled AH, AL, BH, BL, CH, CL, DH &
DL
 These registers can be used individually
for temporary storage of 8-bit data.
 The AL register is also called the
accumulator
 Certain pairs of these general purpose
registers can be used together to store 16-
bit data words
 AH-AL pair --- AX register
 BH-BL pair --- BX register
 CH-CL pair --- CX register
 General Purpose Registers (S – 2)

 AX Register: AX register is also known as accumulator

register that stores operands for arithmetic operation like
divided, rotate.
 BX Register: This register is used as an offset storage for
forming physical addresses in case of certain addressing
modes.
 CX Register: It is used as a default counter in case of string
and loop instructions.
 DX Register: DX register is used to contain I/O port address
for I/O instruction.
Pointer and Index Registers (S – 2)

 Stack Pointer (SP)

 Base Pointer (BP)
 Source Index (SI)
 Destination Index (DI)
 Pointer and Index Registers (S – 2)
 Stack Pointer (SP):
 The function of SP is same as the function of SP in Intel
8085.
 It stores the address of top element in the stack.

 BP, SI & DI are used

 for temporary data storage just as the general purpose

registers

 in memory address computation. (later)

 Base Pointer (BP), Source Index (SI),
Destination Index (DI) Registers (S – 2)
 BP : We can use it instead of SP for accessing the stack using
based addressing mode.
 In this case, the 20-bit physical stack address is calculated from
BP and SS
 SI : It can be used to hold the offset of source data in the data
segment
 In this case, the 20-bit physical data address is calculated from SI
and DS
 DI: It is used to store the offset of destination in data or extra
segment
 String instructions always use ES and DI to determine the 20-bit
physical address for the destination
 Stack Pointer Register (S – 2)
 The SP register in the EU
holds the 16-bit offset from
the start of the stack
segment to the top of the
stack
 For stack operation, the
content of the SS register
and the content of the SP
register are used to produce
the 20-bit physical address.
Instruction Pointer (IP) (S – 2)
 The Instruction Pointer (IP) in
8086 acts as a Program
Counter.
 IP register holds the 16-bit
address or offset of the next
code byte within the code
segment
 The value contained in the IP
is referred to as an offset
because the 20-bit physical
code byte address is
calculated from IP and CS
Cont. (S – 2)

 The instruction pointer register contains a 16-bit offset

which tells, where in that 64-Kbyte code segment the
next instruction byte is to be fetched from.
Thank You