UNIT-1

Microprocessors and
Microcontrollers

1
UNIT-I:8085 Microprocessor: Evolution of
microprocessors, The 8085 Microprocessor,
Microprocessor communication and bus
timings, Generating control signals, 8085
MPU and its architecture and pin diagram,
Decoding and Executing an Instruction,
Instruction set and Assembly Language
programming.

2
Brief Discussion

• What is Computer?

– CPU -> CU + ALU + registers

– Memory -> RAM/ ROM
– I/P AND O/P DEVICES

3
 What is Microprocessor?
– 1960s’ CPU – designed with logic gates
– LSI – Large Scale Integration
– SSI to LSI – called Microprocessor
– Microcomputer
– Intel – 4 bit microprocessor 4004 in 1971
– 8 bit microprocessor 8080
– 8-bit 8085 (8 bit data bus + 16 bit address bus)
– 16-bit 8086 (16 bit data bus + 20 bit address
bus)
– 16 bit processors – 8088,80186,80188, 80286
– 32 bit processors – 80386 , 80486, 80586 (P)
4
 Microprocessor
 Microprocessor is a brain of computer.
 It is a single chip which is capable of processing data.
 It controls all components like memory, I/O,External
devices.
 It executes sequence of instructions.
 Microprocessor fetch, decode and execute the
instructions.
 Internal Architecture of Microprocessor is complex.

5
 Historical Background
• First generation (1939-1954)-Vaccum tubes
• Second generation (1954-1959)- Invention of
Transistor->Bell Laborites
• Third generation (1959-1971)- Invention of Integrated
Circuit
• Fourth generation (1971-present)- Development of First
Microprocessor
• Developed by Intel
-> 4004 “cpu-on-a-chip”.
• 1976- Introduction of Microcontroller
Developed by Intel
->8048 “computer-on-a-chip”.
6
 Applications
• General Purpose µp
-> Desktop, PCs, Laptops, Workstations,
Servers.

• Microcontrollers: Embedded Systems

->Consumer Electronics: Toys, Cameras,
Robots.

->Consumer Products: Washing Machines,

Microwave Ovens.
Contd… 7
Microprocessor Applications
->Instrumentation: Oscilloscopes, Medical
Instruments.

-> Communications: Telephone Sets, Cordless

Phones.

->Office: FAX Machines, Printers.

->Multimedia Applications: Cell Phones,

Teleconferencing.
8
Evolution of Microprocessors

 Introduction
 4-Bit Microprocessors
 8-Bit Microprocessors
 16-Bit Microprocessors
 32-Bit Microprocessors
 64-Bit Microprocessors
2
INTRODUCTION
 Fairchild Semiconductors (founded in 1957)
invented the first IC in 1959.
 In 1968, Robert Noyce, Gordan Moore, Andrew
Grove resigned from Fairchild Semiconductors.
 They founded their own company Intel (Integrated
Electronics).
 Intel grown from 3 man start-up in 1968 to industrial
giant by 1981.
 It had 20,000 employees and $188 million revenue. 3
4-BIT MICROPROCESSORS

4
INTEL
4004
 Introduced in 1971.
 It was the first
microprocessor by Intel.
 It was a 4-bit µP.
 Its clock speed was
740KHz.
 It had 2,300
transistors.
 It could execute around
60,000 instructions per 5
second.
INTEL
4040
 Introduced in 1974.
 It was also 4-bit µP.

6
8-BIT MICROPROCESSORS

7
INTEL
8008
 Introduced in 1972.
 It was first 8-bit µP.
 Its clock speed was 500
KHz.
 Could execute 50,000
instructions per second.

8
INTEL
8080
 Introduced in 1974.
 It was also 8-bit µP.
 Its clock speed was 2
MHz.
 It had 6,000
transistors.
 Was 10 times faster
than
8008.
9
 Could execute 5,00,000
instructions per
  Introduced in 1976.
INTEL 8085  It was also 8-bit µP.
 Its clock speed was 3 MHz.
 Its data bus is 8-bit and
address bus is 16-bit.
 It had 6,500
transistors.
 Could execute 7,69,230
instructions per
second.
 It could access 64 KB
of
 memory.
Over 100 million copies 10
 Itwere
had sold.
246 instructions.
16-BIT MICROPROCESSORS

11
  Introduced in 1978.

INTEL 8086  It was first 16-bit µP.

 Its clock speed is 4.77 MHz, 8
MHz and 10 MHz, depending on
the version.
 Its data bus is 16-bit and
address bus is 20-bit.
 It had 29,000
transistors.
 Could execute 2.5 million
instructions per second.
 It could access 1 MB of
memory.

 It had
It had Multiply
22,000 and Divide 12
instructions.
instructions.
INTEL
8088
 Introduced in 1979.
 It was also 16-bit µP.
 It was created as a cheaper
version of Intel’s 8086.
 It was a 16-bit processor
with an 8-bit external bus.
 Could execute 2.5 million
instructions per second.
 This chip became the most
popular in the computer
industry when IBM used it 13
for first PC.
its
INTEL 80186 & 80188
 Introduced in 1982.
 They were 16-bit µPs.
 Clock speed was 6 MHz.
 80188 was a cheaper
version of 80186 with an 8-
bit external data bus.
 They had additional
components like:
 Interrupt Controller
 Clock Generator
 Local Bus Controller
14
 Counters
INTEL
80286
 Introduced in 1982.
 It was 16-bit µP.
 Its clock speed was 8 MHz.
 Its data bus is 16-bit and
address bus is 24-bit.
 It could address 16 MB
of
memory.
 It had 1,34,000
 It could execute 4 million
transistors. 15
instructions per second.
32-BIT MICROPROCESSORS

16
  Introduced in 1986.
INTEL  It was first 32-bit µP.
80386  Its data bus is 32-bit and
address bus is 32-bit.
 It could address 4 GB of
memory.
 It had 2,75,000
transistors.
 Its clock speed varied from 16
MHz to 33 MHz depending upon
the various versions.
 Different versions:
 80386 DX
 80386 SX
 80386 SL
 Intel 80386 became the best 17
selling microprocessor in history.
INTEL  Introduced in 1989.
80486  It was also 32-bit µP.
 It had 1.2 million transistors.
 Its clock speed varied from
16 MHz to 100 MHz
depending upon the various
versions.
 It had five different versions:
 80486 DX
 80486 SX
 80486 DX2
 80486 SL
 80486 DX4
 8 KB of cache memory was
introduced. 18
  Introduced in 1993.
INTEL PENTIUM  It was also 32-bit µP.
 It was originally named 80586.
 Its clock speed was 66 MHz.
 Its data bus is 32-bit and
address bus is 32-bit.
 It could address 4 GB of
memory.
 Could execute 110
million
instructions per second.
 Cache memory:
 8 KB for instructions.

19
8 KB for data.
INTEL PENTIUM
PRO
 Introduced in 1995.
 It was also 32-bit µP.
 It had L2 cache of 256 KB.
 It had 21 million transistors.
 It was primarily used in
server systems.
 Cache memory:
 8 KB for instructions.
 8 KB for data.
20
 It had L2 cache of 256
KB.
INTEL PENTIUM
II
 Introduced in 1997.
 It was also 32-bit µP.
 Its clock speed was 233
MHz to 500 MHz.
 Could execute 333 million
instructions per second.
 MMX technology was
supported.
 L2 cache & processor
were on one circuit. 21
INTEL PENTIUM II
XEON
 Introduced in 1998.
 It was also 32-bit µP.
 It was designed for servers.
 Its clock speed was 400
MHz to 450 MHz.
 L1 cache of 32 KB & L2
cache of 512 KB, 1MB or
2 MB.
 It could work with 4 Xeons
in same system. 22
INTEL PENTIUM
III
 Introduced in 1999.
 It was also 32-bit µP.
 Its clock speed varied
from 500 MHz to 1.4
GHz.
 It had 9.5 million
transistors.

23
INTEL PENTIUM
IV
 Introduced in 2000.
 It was also 32-bit µP.
 Its clock speed was from
1.3 GHz to 3.8 GHz.
 L1 cache was of 32 KB &
L2 cache of 256 KB.
 It had 42 million
transistors.
 All internal connections
were made from aluminium 24
to copper.
INTEL DUAL  Introduced in 2006.
CORE  It is 32-bit or 64-bit µP.
 It has two cores.
 Both the cores have there
own internal bus and L1
cache, but share the
external bus and L2 cache
(Next Slide).
 It supported SMT
technology.
 SMT: Simultaneously Multi-
Threading
 E.g.: Adobe Photoshop
25
supported SMT.
33
64-BIT MICROPROCESSORS

34
INTEL CORE
2
 Introduced in 2006.
 It is a 64-bit µP.
 Its clock speed is from
1.2 GHz to 3 GHz.
 It has 291 million
transistors.
 It has 64 KB of L1 cache
per core and 4 MB of L2
cache.
 It is launched in three different
versions:
 Intel Core 2 Duo
28
 Intel Core 2 Quad
 Intel Core 2 Extreme
INTEL CORE
I7

 Introduced in 2008.
 It is a 64-bit µP.
 It has 4 physical cores.
 Its clock speed is from
2.66 GHz to 3.33 GHz.
 It has 781 million
• transistors.
 It has 64 KB of L1
cache per core, 256
KB of L2 cache and298
MB of L3 cache.
INTEL CORE
I5

 Introduced in 2009.
 It is a 64-bit µP.
 It has 4 physical cores.
 Its clock speed is from
2.40 GHz to 3.60 GHz.
 It has 781 million
• transistors.
 It has 64 KB of L1
cache per core, 256
KB of L2 cache and308
MB of L3 cache.
INTEL CORE
I3

 Introduced in 2010.
 It is a 64-bit µP.
 It has 2 physical cores.
 Its clock speed is from
2.93 GHz to 3.33 GHz.
 It has 781 million
• transistors.
 It has 64 KB of L1
cache per core, 512
KB of L2 cache and314
MB of L3 cache.
Basic Concepts of Microprocessors
Differences between:

– Microcomputer – a computer with a

microprocessor as its CPU. Includes memory, I/O
etc.

– Microprocessor – silicon chip which includes ALU,

register circuits & control circuits

– Microcontroller – silicon chip which includes

microprocessor, memory & I/O in a single package.
39
Definition of the Microprocessor
• The microprocessor is a programmable device
that takes in numbers, performs on them
arithmetic or logical operations according to the
program stored in memory and then produces
other numbers as a result.

40
The Salient Features of 8085 Microprocessor:

• It was introduced in 1977 and it is an 8 bit processor.

• It is a single chip N-MOS device with 40 pins and
contains 6200 transistors approx.
• It has multiplexed address and data bus.(AD0-AD7).
• It works on 5 Volt dc power supply.
• The maximum clock frequency is 3 MHz while
minimum frequency is 500kHz.
• It provides 74 instructions with 5 different addressing
modes.
The Salient Features of 8085 Microprocessor:

• It provides 16 address lines so it can access 2^16

=64K bytes of memory.
• It generates 8 bit I/O address so it can access
2^8=256 input ports.
• It provides 5 hardware interrupts:TRAP, RST 5.5,
RST 6.5, RST 7.5,INTR.
• It provides Acc ,one flag register ,6 general purpose
registers and two special purpose registers(SP,PC).
• It provides serial lines SID ,SOD.So serial
peripherals can be interfaced with 8085 directly.
42
• System Bus – wires connecting memory & I/O to
Microprocessor
– Address Bus
• Unidirectional
• Identifying peripheral or memory location
– Data Bus
• Bidirectional
• Transferring data
– Control Bus
• Synchronization signals
• Timing signals
• Control signal
43
Architecture of 8085A

44
 Intel 8085 Microprocessor
• Microprocessor consists of five essential blocks.
(1) Arithmetic Logic Section
(2) Register Section
(3) The Interrupt Control Section
(4) Serial I/O Section
(5) The Timing And Control Unit
(1) Arithmetic & Logic Section: This section consists of:
(a) Accumulator (A)
(b) Temporary Register (TR)
(c) Flag Register (FR)
(d) Arithmetic Logic Unit (ALU)

45
Special purpose Register (Accumulator)
Arithmetic and/or logic operations on one or two operations are the basic
data transformations implemented in a μρ one of thesetwo operands is
always in the accumulator.
Accumulator is an 8-bit register accessible to the user is connected to the
8-bit internal data bus.

Temporary registrar (TR):

This is an 8-bit register not accessible to the user. It is used by
the processor for internal operations. The second operand as and
when necessary is loaded in to this register by the microprocessor
before the desisted operation takes placed in the ALU.

Arithmetic Logical Unit (ALU):

The various arithmetic and logical operations that can be performed by
ALU are:
 Binary addition, subtraction, increment and decrement,
 Logical AND, OR and EX-OR,
 Complement,
 Rotate left of right. 46
If the accumulator holds on an even number of 1’s, it is said that even
parity exists and the parity flag is set to ‘1’. However, if the accumulator holds an odd
number of ‘1’ it is called odd parity and the parity flag is reset to ‘0’. 47
Example 1:
Let us consider the execution of the instruction ADD B. ADD is the mnemonic for
addition. The first operand is known to exist in the accumulator (Reg. A). Register
B contains the second operand.
The meaning of the instruction is add the contents of the B register to the contents of
A register and store the result back in the accumulator (A). Symbolically we can
write,(A) (A) + (B)
Let as suppose the register contents are (A) = 9BH, (B) = A5H before the execution of
the instruction. It means,
(A) = 9BH → (1001 1011)2
(B) = A5H → (1010 0101)2
ADD B = (A+B) → (0100 0000)2
As a result of addition, there is a carry from b3 to b4 position and therefore AC is set.
Also there is a carry from the MSB out and, therefore, CY flag is also set.
Soon after the execution of ADD B instruction the accumulator contains (A) = (0100
0000)2 = 40H and is non-zero. Therefore Z flag is reset to zero. Also, result
contains only
• one ‘1’, an odd number. Therefore, parity bit is also be reset to zero.
• Since the MSB of the result is zero, therefore the sign (S) bit is also reset. Thus
the flag register, soon after the execution of the instruction, contains (0001 0001)2
= 11H. 48
(2) Register Section
General Purpose REGISTER SECTION:
• There are six 8-bit general purpose registers designated as
B,C, D, E, H and L. All these registers are accessible to the
user. It means their contents can be read without
destroying it or some new data can be written into it
through instructions.
• The six general purpose registers B, C, D, E, H, L can also
be combined together as register pairs for 16-bit operation
only the following pairs are possible:
i. (B,C) pair with (C) lower order 8-bits and (B) higher order 8-
bits.
ii. (D,E) pair with (E) lower order 8-bits and (D) higher order 8-
bits.
iii. (H,L) pair with (L) lower order 8-bits and (H) higher order 8-
bits. 49
• PROGRAM COUNTER:
This is a 16-bit register accessible to the user. It is a special
purpose register and it always contains the address of the
next instruction to be fetched from the program memory
and executed by the CPU in a program sequence.
• STACK POINTER REGISTER:
• The stack is a storage area of the processor. It is 16-
bit register itself. Whenever an instruction refers to the
register pair (B,C), (D,E), (H,L) or (SPH,SPL), an 8-bit code
RP is used in the operation code to identify the register
pairs.
(RP)
00 (B,C)
01 (D,E)
10 (H,L)
11 (SPH,SPL) 50
W-Z:
(W) and (Z) are two 8-bit temporary registers not accessible to
the user. They are exclusively used for the internal operation
by the microprocessor.
Increment-Decrement Address Latch:
• It is another 16-bit internal register latch available in the
register section for internal operations and is not accessible
to the user. The address latch serves two functions.
Instruction Register & Instruction Decoder:
• The first word of an instruction is the operation code, i.e.,
binary code for that instruction. Therefore, in the first
machine cycle of any instruction μ𝑝 fetches the instruction
from the memory. The op-code representing the instruction
to be executed is fetched from the (program) memory
location pointed to by (PC) and loaded into the instruction
register (IR). 51
(3) Interrupt Control Section:
• Sometimes it is necessary to interrupt the execution of the main program
to answer a request from an I/O device.
(4) Serial I/O Control:
• Sometimes, I/O devices work with serial data rather than
parallel. In this case, the serial data stream from an input device must be
converted to 8-bit parallel data before the computer can use it.
• The SID (Serial Input Data) input is where serial data enters the 8085A.
The SOD (Serial Output Data) output is where the serial data leaves the
8085A.
(5) Timing and Control section:

𝜇𝑝. The on-chip clock oscillator which produces the internal clock is a
• The timing and control section supervise the complete operation of the

part of this section. The timing and control section also has a state
generator circuit to generate 10 different states namely T1, T2, T3, T4,
T5, T6, TRESET, THALT, TWAIT and THOLD.
• The instruction fetch portion of an instruction cycle requires a machine
cycle for each byte of the instruction to be fetched. Since an instruction
consists of 1 to 3 bytes (1, 2 or 3), the instruction fetch is one to three
52
machine cycles in duration.
 Pin Diagram of 8085

Interrupts

53
 X1 & X2
Pin 1 and Pin 2 (Input)
 These are also called
Crystal Input Pins.

 8085 can generate

clock signals
internally.

 To generate clock
signals internally,
8085 requires external
inputs from X1 and X2.

5
4
 RESET IN and RESET OUT
Pin 36 (Input) and Pin 3 (Output)
 RESET IN:

◦ It is used to reset the

microprocessor.

◦ It is active low
signal.

◦ When the signal on this

pin is low for at least 3
clocking cycles, it
forces the
microprocessor to
reset itself.
5
5
 RESET IN and RESET OUT
Pin 36 (Input) and Pin 3 (Output)
 Resetting the
microprocessor means:

◦ Clearing the PC and IR.

◦ Disabling all interrupts
(except TRAP).
◦ Disabling the SOD
pin.
◦ All the buses (data,
address, control) are tri-
stated.
◦ Gives HIGH output to
RESET OUT pin.
5
6
 RESET IN and RESET OUT
Pin 36 (Input) and Pin 3 (Output)
 RESET OUT:

◦ It is used to reset the

peripheral devices and
other ICs on the circuit.

◦ It is an output signal.

◦ It is an active high signal.

◦ The output on this pin goes

high whenever RESET IN is
given low signal.

◦ The output remains high as

long as RESET IN is kept low.
5
7
 SID and SOD
Pin 4 (Input) and Pin 5 (Output)
 SID(Serial Input
Data):

o It takes 1 bit input from

serial port of 8085.

o Stores the bit at the 8th

position (MSB) of the
Accumulator.

o RIM (Read Interrupt

Mask) instruction is

58
 SID and SOD
Pin 4 (Input) and Pin 5 (Output)
 SOD (Serial Output
Data):

o It takes 1 bit from

Accumulator to serial port
of 8085.

o Takes the bit from the 8th

position (MSB) of the
Accumulator.

o SIM (Set Interrupt

Mask) instruction is
used to
59
 Interrupt Pins
 Interrupt:

• It means interrupting the normal execution of the

microprocessor.

• When microprocessor receives interrupt signal,

it discontinues whatever it was executing.

• It starts executing new program indicated by the

interrupt signal.

• Interrupt signals are generated by external peripheral

devices.

• After execution of the new program, microprocessor

goes back to the previous program.
12
 Sequence of Steps Whenever There
is an Interrupt
 Microprocessor completes execution of current
instruction of the program.

 PC contents are stored in stack.

 PC is loaded with address of the new program.

 After executing the new program, the

microprocessor returns back to the previous
program.

 It goes to the previous program by reading the

top value of stack.
61
Five Hardware Interrupts in 8085
 TRAP

 RST 7.5

 RST 6.5

 RST 5.5

 INTR

62
 Classification of Interrupts
 Maskable and Non-Maskable

 Vectored and Non-Vectored

 Edge Triggered and Level Triggered

 Priority Based Interrupts

63
 Maskable Interrupts
 Maskable interrupts are those
interrupts which can be enabled or
disabled.

 Enabling and Disabling is done by

software instructions.

64
 Vectored Interrupts
 Theaddresses to which program
control goes:
Name Vectored Address

RST 7.5 003C H (7.5 x 0008 H)

RST 6.5 0034 H (6.5 x 0008 H)

RST 5.5 002C H (5.5 x 0008 H)

TRAP 0024 H (4.5 x 0008 H)

Absolute address is calculated by
multiplying the RST value with 0008 H.
65
 Priority Based Interrupts
Priority of interrupts:

Interrupt Priority

TRAP 1
RST 7.5 2
RST 6.5 3
RST 5.5 4
INTR 5

66
Mask Non- Vecto Non- Edge Level Both Priority
able Mask red Vecto Trigg Trigg Edge
Int able Int red ered ered and
Int Int Level
Triggere
d

INTR TRAP RST INTR RST7. RST TRAP TRAP-1

7.5 5 6.5

RST RST RST RST 7.5-2

7.5 6.5 5.5

RST RST RST 6.5-3

6.5 5.5

RST TRAP RST 5.5-4

5.5

INTR-5
 INTA
Pin 11 (Output)
 It stands for interrupt
acknowledge.
 It is an out going
signal.
 It is an active
signal.
low
Low output on this pin
indicates that
microprocessor has
acknowledged the
INTR request.

68
 Address and Data Pins
 Address Bus:

• The address bus is used to send

address to memory.
• It selects one of the many locations in
memory.
• Its size is 16-bit.

69
 Address and Data Pins
 Data Bus:

• It is used to transfer data between

microprocessor and memory.
• Data bus is of 8-bit.

70
 AD0 – AD7
Pin 19-12 (Bidirectional)
 These pins serve the dual
purpose of transmitting lower
order address and data
byte.

 During 1st clock cycle, these

pins act as lower half of
address.

 In remaining clock cycles,

these pins act as data bus.

 The separation of lower order

address and data is done by
address latch.
71
 A8 – A15
Pin 21-28 (Unidirectional)
 These pins carry the
higher order of address
bus.

 The address is sent from

microprocessor to
memory.

 These 8 pins are switched

to high impedance state
during HOLD and RESET
mode.

72
 ALE
Pin 30 (Output)
 It is used to enable Address
Latch.

 It indicates whether bus

functions as address bus or
data bus.

 If ALE = 1 then
◦ Bus functions as address
bus.

 If ALE = 0 then
◦ Bus functions as data bus.

73
 S0 and S1
Pin 29 (Output) and Pin 33 (Output)
 S0 and S1 are called Status
Pins.

 They tell the current

operation which is
in progress in 8085.
S0 S1 Operation

0 0 Halt
0 1 Write
1 0 Read
1 1 Opcode Fetch
74
 IO/M
Pin 34 (Output)
 This pin tells whether I/O
or memory operation is
being performed.

 If IO/M = 1 then
◦ I/O operation is
being
performed.

 If IO/M = 0 then
◦ Memory operation is
being performed.
75
 IO/M
Pin 34 (Output)
 The operation being performed is indicated
by S0 and S1.

 If S0 = 0 and S1 = 1 then
◦ It indicates WRITE operation.

 If IO/M = 0 then
◦ It indicates Memory operation.

 Combining these two we get Memory

Write
Operation. 76
 Table Showing IO/M, S0, S1 and
Corresponding Operations

Operations IO/M S0 S1

Opcode Fetch 0 1 1

Memory Read 0 1 0

Memory Write 0 0 1

I/O Read 1 1 0
I/O Write 1 0 1
Interrupt Ack. 1 1 1

Halt High Impedance 0 0

77
 RD
Pin 32 (Output)
 RD stands for Read.
 It is an active low signal.
 It is a control signal used
for Read operation either
from memory or from Input
device.
 A low signal indicates that
data on the data bus
must be placed either
from selected memory
location or from input
device.

78
 WR
Pin 31 (Output)
 WR stands for Write.
 It is also active low signal.
 It is a control signal used
for Write operation either
into memory or into output
device.
 A low signal indicates that
data on the data bus
must be written into
selected memory location
or into output device.

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 READY
Pin 35 (Input)
 This pin is used to
synchronize slower
peripheral devices with
fast microprocessor.
 A low value causes the
microprocessor to enter
into wait state.
 The microprocessor
remains in wait state
until the input at this pin
goes high.
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 HOLD
Pin 38 (Input)
 HOLD pin is used to request
the microprocessor for
DMA transfer.
 A high signal on this pin is a
request to microprocessor to
relinquish the hold on
buses.
 This request is sent by DMA
controller.
 Intel 8257 and Intel 8237 are
two DMA controllers.

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 HLDA
Pin 39 (Output)
 HLDA stands for Hold
Acknowledge.
 The microprocessor uses this
pin to acknowledge the receipt
of HOLD signal.
 When HLDA signal goes high,
address bus, data bus, RD,
WR, IO/M pins are tri-stated.
 This means they are cut-off
from external environment.

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 HLDA
Pin 39 (Output)
 The control of these
buses goes to
DMA Controller.
 Control remains at
DMA Controller until
HOLD is held high.
 When HOLD goes
low, HLDA also goes
low and the
microprocessor takes
control of the buses.
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 VSS and VCC
Pin 20 (Input) and Pin 40 (Input)
+5V power supply is
connected to VCC.

Ground signal is
connected to VSS.

84
Microprocessor Communication
and bus timings

85
Timing Diagram

86
Ex:Iiiustrate the steps and the timing of data flow when the
instruction code 0100 1111 (4FH-MOV C,A) stored in location
2005H is being fetched.

1.The program counter places the 16-bit memory address on

the address bus.
2. The control unit sends the control signal read to enable the
memory chip.
3.The byte from the memory location is placed on the data
bus.
4. The byte is placed in the instruction decoder by the
instruction decoder and the contents of the accumulator are
copied in to register C.The task is performed during the T4.

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Generating control signals

88
Case(i): IO/=1, =0,=1
Case(ii): IO/=1, =1,=0
Case(iii):IO/=0, =0,=1
Case(iv):IO/=0, =1,=0

If Latch=Enable ;Address lines A0-A7

Latch=Disable; Data lines D0-D7

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Decoding and Executing an
Instruction

90
Assme that the accumulator contains data byte 82H, and
the instruction MOV C,A (4FH) is fetched list the steps in
decoding and executing the instruction.

1. The contents of the data bus (4F) are placed in the

instruction register and decoded.
2. 2. The contents of the accumulator (82H) are
transferred to the temporary register in the ALU.
3. The contents of the temporary register are transferred
to register C

91
92
Memory READ Machine Cycle:

93
94
Memory WRITE Machine Cycle:

95
 Addressing modes
Every instruction of a program has to operate on a data. The
method of specifying the data to be operated by the instruction is
called Addressing. The 8085 has the following 5 different types
of addressing.
1. Immediate Addressing
2. Direct Addressing
3. Register Addressing
4. Register Indirect Addressing
5. Implied Addressing

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1. Immediate Addressing: In immediate addressing mode, the
data is specified in the instruction itself. The data will be a
part of the program instruction.
EX. MVI B, 3EH - Move the data 3EH given in the instruction
to B register; LXI SP, 2700H.
2. Direct Addressing: In direct addressing mode, the address of
the data is specified in the instruction. The data will be in
memory. In this addressing mode, the program instructions and
data can be stored in different memory.
EX. LDA 1050H - Load the data available in memory location
1050H in to accumulator; SHLD 3000H 19
3. Register Addressing: In register addressing mode, the
instruction specifies tthe name of the register in which the data
is available.
EX. MOV A, B - Move the content of B register to A register;
SPHL; ADD C 97
4. Register Indirect Addressing: In register indirect addressing
mode, the instruction specifies the name of the register in
which the address of the data is available. Here the data will
be in memory and the address will be in the register pair.

EX. MOV A, M - The memory data addressed by H L pair is

moved to A register. LDAX B.

5. Implied Addressing: In implied addressing mode, the

instruction itself specifies the data to be operated.

EX. CMA - Complement the content of accumulator; RAL

98
 Instruction set
The programmer can write a program in assembly
language using these instructions. These instructions
have been classified into the following groups:
1. Data Transfer Group
2. Arithmetic Group
3. Logical Group
4. Branch Control Group
5. I/O and Machine Control Grou

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1.Data Transfer Group
1. MOV r1, r2 (Move Data; Move the content of the one register to
another). [r1] <-- [r2]
2. MOV r, m (Move the content of memory register). r <-- [M]
3. MOV M, r. (Move the content of register to memory). M <-- [r]
4. MVI r, data. (Move immediate data to register). [r] <-- data.
5. MVI M, data. (Move immediate data to memory). M <-- data.
6. LXI rp, data 16. (Load register pair immediate). [rp] <-- data 16
bits, [rh] <-- 8 LSBs of data.
7. LDA addr. (Load Accumulator direct). [A] <-- [addr].
8. STA addr. (Store accumulator direct). [addr] <-- [A].
9. LHLD addr. (Load H-L pair direct). [L] <-- [addr], [H] <--
[addr+1].

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1.Data Transfer Group

10. SHLD addr. (Store H-L pair direct) [addr] <-- [L], [addr+1] <--
[H].
11. LDAX rp. (LOAD accumulator indirect) [A] <-- [[rp]] 13
12. STAX rp. (Store accumulator indirect) [[rp]] <-- [A].
13. XCHG. (Exchange the contents of H-L with D-E pair) [H-L] <-->
[D-E]
14. IN 8bit port address-Read data from the input port.
15. OUT 8bit port address-Write data from the output port.

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2. Arithmetic Group
1. ADD r. (Add register to accumulator) [A] <-- [A] + [r].
2. ADD M. (Add memory to accumulator) [A] <-- [A] + [[H-L]].
3. ADC r. (Add register with carry to accumulator). [A] <-- [A] + [r] + [CS].
4. ADC M. (Add memory with carry to accumulator) [A] <-- [A] + [[H-L]]
[CS].
5. ADI data (Add immediate data to accumulator) [A] <-- [A] + data.
6. ACI data (Add with carry immediate data to accumulator). [A] <-- [A] + data
+ [CS].
7. DAD rp. (Add register paid to H-L pair). [H-L] <-- [H-L] + [rp].
8. SUB r. (Subtract register from accumulator). [A] <-- [A] – [r].
9. SUB M. (Subtract memory from accumulator). [A] <-- [A] – [[H-L]].
10. SBB r. (Subtract register from accumulator with borrow). [A] <-- [A] – [r] –
[CS].
11. SBB M. (Subtract memory from accumulator with borrow). [A] <-- [A] –
[[H-L]] – [CS].
12. SUI data. (Subtract immediate data from accumulator) [A] <-- [A] – data.
13. SBI data. (Subtract immediate data from accumulator with borrow). [A] <- -
102
[A] – data – [CS].
14. INR r (Increment register content) [r] <-- [r] +1.
15. INR M. (Increment memory content) [[H-L]] <-- [[H-L]] +
1.
16. DCR r. (Decrement register content). [r] <-- [r] – 1.
17. DCR M. (Decrement memory content) [[H-L]] <-- [[H-L]] –
1.
18. INX rp. (Increment register pair) [rp] <-- [rp] – 1. 19. DCX
rp (Decrement register pair) [rp] <-- [rp] -1.
20. DAA (Decimal adjust accumulator)

103
3. Logical Group
1. ANA r. (AND register with accumulator) [A] <-- [A] ^ [r].
2. ANA M. (AND memory with accumulator). [A] <-- [A] ^ [[H-L]].
3. ANI data. (AND immediate data with accumulator) [A] <-- [A] ^ data.
4. ORA r. (OR register with accumulator) [A] <-- [A] v [r].
5. ORA M. (OR memory with accumulator) [A] <-- [A] v [[H-L]]
6. ORI data. (OR immediate data with accumulator) [A] <-- [A] v data.
7. XRA r. (EXCLUSIVE – OR register with accumulator) [A] <-- [A] v [r]
8. XRA M. (EXCLUSIVE-OR memory with accumulator) [A] <-- [A] v [[H-L]]
9. XRI data. (EXCLUSIVE-OR immediate data with accumulator) [A] <-- [A]
10. CMA. (Complement the accumulator) [A] <-- [A]
11. CMC. (Complement the carry status) [CS] <-- [CS]
12. STC. (Set carry status) [CS] <-- 1.
13. CMP r. (Compare register with accumulator) [A] – [r]
14. CMP M. (Compare memory with accumulator) [A] – [[H-L]]
15. CPI data. (Compare immediate data with accumulator) [A] – data

104
16. RLC (Rotate accumulator left) [An+1] <-- [An], [A0] <-- [A7],
[CS] <-- [A7]

17. RRC. (Rotate accumulator right) [A7] <-- [A0], [CS] <-- [A0], [An] <-- [An+1].

18. RAL. (Rotate accumulator left through carry) [An+1] <-- [An], [CS] <-- [A7], [A0]
<-- [CS].
19. RAR. (Rotate accumulator right through carry) [An] <-- [An+1], [CS] <-- [A0],
[A7] <-- [CS]

105
4. Branch Group
1. JMP addr (label). (Unconditional jump: jump to the instruction specified by
the address). [PC] <-- Label.
2. Conditional Jump addr (label): After the execution of the conditional jump
instruction the program jumps to the instruction specified by the address (label)
if the specified condition is fulfilled.
1. JZ addr (label). (Jump if the result is zero)
2. 2. JNZ addr (label) (Jump if the result is not zero)
3. 3. JC addr (label). (Jump if there is a carry)
4. 4. JNC addr (label). (Jump if there is no carry)
5. 5. JP addr (label). (Jump if the result is plus)
6. 6. JM addr (label). (Jump if the result is minus)
7. 7. JPE addr (label) (Jump if even parity)
8. 8. JPO addr (label) (Jump if odd parity)
3. CALL addr (label) (Unconditional CALL: call the subroutine identified by
the operand)
4. RET (Return from subroutine)
106
5. Stack, I/O and Machine Control Group
1. IN port-address. (Input to accumulator from I/O port) [A] <-- [Port]
2. OUT port-address (Output from accumulator to I/O port) [Port] <-- [A]
3. PUSH rp (Push the content of register pair to stack)
4. PUSH PSW (PUSH Processor Status Word)
5. POP rp (Pop the content of register pair, which was saved, from the stack)
6. POP PSW (Pop Processor Status Word)
7. HLT (Halt)
8. XTHL (Exchange stack-top with H-L)
9. SPHL (Move the contents of H-L pair to stack pointer)
10. EI (Enable Interrupts)
11. DI (Disable Interrupts)
12. SIM (Set Interrupt Masks)
13. RIM (Read Interrupt Masks)
14. . NOP (No Operation)

107
Assembly Language
programming
1) Addition program:
Solution1:
MVI A,34H
MVI B,45H
ADD B
HLT

Solution 2:
LDA 2000
MOV B,A
LDA 2001
ADD B
STA 2003
HLT

2)A&=NOT(1<<5) WHERE A=72

108