CS 140 Lecture 11

Sequential Networks: Timing and

Retiming
Professor CK Cheng
CSE Dept.
UC San Diego

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 Sequential Networks

Timing: Setup Time and Hold Time Constraints

D Q

Q’

CLK

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Sequential Networks

A B C D

Combinational

CLK CLK

A typical sequential network has both a

combinational circuit and flip-flips.

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A B C
Combinational

CLK CLK

tcq + tcomb + tsetup < T

Clock period
thold < tcq + tcomb
Shortest path

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 Input Timing Constraints
• Setup time: tsetup = time before the clock edge that
data must be stable (i.e. not changing)
• Hold time: thold = time after the clock edge that data
must be stable
• Aperture time: ta = time around clock edge that data
must be stable (ta = tsetup + thold)
CLK

tsetup thold

ta 5
 Output Timing Constraints
• Propagation delay: tpcq = time after clock edge that
the output Q is guaranteed to be stable (i.e., to stop
changing)
• Contamination delay: tccq = time after clock edge that
Q might be unstable (i.e., start changing)
CLK

tccq
tpcq

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 Dynamic Discipline
• The delay between registers has a minimum and
maximum delay, dependent on the delays of the
circuit elements
CLK CLK
Q1 CL D2

R1 R2
(a)
Tc
CLK

Q1

D2
(b)
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 Setup Time Constraint
• The setup time constraint depends on the maximum
delay from register R1 through the combinational logic.
• The input to register R2 must be stable at least tsetup
before the clock edge.
CLK CLK
Q1 C
L
D2
Tc ≥ tpcq + tpd + tsetup
R1 R2

CLK
Tc
tpd ≤ Tc – (tpcq + tsetup)
Q1

D2
tpcq tpd tsetup

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 Hold Time Constraint
• The hold time constraint depends on the minimum delay
from register R1 through the combinational logic.
• The input to register R2 must be stable for at least thold
after the clock edge.
CLK CLK
Q1 C
L
D2
thold < tccq + tcd
R1 R2

CLK
tcd > thold - tccq
Q1

D2
tccq tcd
thold

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 Timing Analysis
Timing Characteristics
tccq = 30 ps
CLK CLK
tpcq = 50 ps
A
tsetup = 60 ps
B
thold = 70 ps
X' X
C

Y' Y
D tpd = 35 ps
tpd = tcd = 25 ps
tcd =
Setup time constraint: Hold time constraint:

Tc ≥ tccq + tpd > thold ?

fc = 1/Tc =
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 Timing Analysis
Timing Characteristics
tccq = 30 ps
CLK CLK
tpcq = 50 ps
A
tsetup = 60 ps
B
thold = 70 ps
X' X
C

Y' Y
D tpd = 35 ps
tpd = 3 x 35 ps = 105 ps tcd = 25 ps
tcd = 25 ps
Setup time constraint: Hold time constraint:

Tc ≥ (50 + 105 + 60) ps = 215 ps tccq + tpd > thold ?

fc = 1/Tc = 4.65 GHz (30 + 25) ps > 70 ps ? No!

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 Fixing Hold Time Violation
Timing Characteristics
Add buffers to the short paths:
tccq = 30 ps
tpcq = 50 ps
CLK CLK
A
tsetup = 60 ps
B thold = 70 ps
X' X
C

D
Y' Y tpd = 35 ps
tpd = tcd = 25 ps
tcd =
Setup time constraint: Hold time constraint:

Tc ≥ tccq + tpd > thold ?

fc =
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 Fixing Hold Time Violation
Add buffers to the short paths: Timing Characteristics
tccq = 30 ps
tpcq = 50 ps
CLK CLK
A
tsetup = 60 ps
B thold = 70 ps
X' X
C

D
Y' Y tpd = 35 ps
tpd = 3 x 35 ps = 105 ps tcd = 25 ps
tcd = 2 x 25 ps = 50 ps
Setup time constraint: Hold time constraint:

Tc ≥ (50 + 105 + 60) ps = 215 ps tccq + tpd > thold ?

fc = 1/Tc = 4.65 GHz (30 + 50) ps > 70 ps ? Yes!

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 Clock Skew
• The clock doesn’t arrive at all registers at the same time
• Skew is the difference between two clock edges
• Examine the worst case to guarantee that the dynamic
discipline is not violated for any register – many
registers in a system!
delay CLK

CLK1 CLK2
Q1 C D2
L

R1 R2

t skew

CLK1

CLK2

CLK
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 Setup Time Constraint with Clock
Skew
• In the worst case, the CLK2 is earlier than CLK1
CLK1 CLK2
Q1 C D2
L

R1 R2
Tc
CLK1
Tc ≥ tpcq + tpd + tsetup +
CLK2

Q1
tskew
D2 tpd ≤ Tc – (tpcq + tsetup +
tpcq tpd tsetup tskew tskew)

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 Hold Time Constraint with Clock
Skew
• In the worst case, CLK2 is later than CLK1

CLK1 CLK2
Q1 C D2
L

R1 R2

CLK1 tccq + tcd > thold +

CLK2
tskew
Q1

D2 tcd > thold + tskew –

tccq tcd
tccq
tskew thold

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 Timing and Retiming
• Retiming: Adjust the clock skew so that
the clock period can be reduced.
• Add a few more examples on timing and
retiming.

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