Module 3

Combinational Logic Circuits

Design Procedure & Implementation of
combinational logic circuits
● Two types of logic circuits
● Combinational logic circuits:
○ Output is a pure function of present input

○ When logic gates are connected together to produce a specified output for certain specified
combination of input variables , with no storage involved, the resulting circuit is in the category of
combinational logic circuits .

○ Operation of a combinational circuit is specified logically by a set of Boolean functions.

● Sequential logic circuits :

○ Output depends on present input & past outputs

○ Needs a memory element ➢ Example : Counter

A combinational circuit consists of i/p variables,logic gates and output variables.
The logic gates accept signals from the inputs and generate signals to the outputs.
Here n input binary variables come from an external source. The m output
variables go to an external destination.
For ‘n’ input variables there are 2n possible combinations of binary input values.
For each possible input combinations there is one and only one possible output
combinations.
Design Procedure
1. The problem is stated.
2. The number of available input variables and required output variables are
determined.
3. The input and output variables are assigned letter symbols.
4. The truth table that defines the required relationships between inputs and
output is derived.
5. The simplified Boolean functions for each output is obtained.
6. The logic diagram is drawn.
Examples of combinational logic circuits
1. Adder
2. Subtractor
3. Multiplexer
4. Demultiplexer
5. Encoder
6. Decoder
ADDERS
• A digital circuit that performs addition of numbers.
• There are two types of adders
1. Half Adder
2. Full Adder
HALF ADDER
Adds two binary digits giving a sum bit and a carry bit.
• Logic Symbol
TRUTH TABLE
•Logic Expression
From truth table,
1. C is 1 when both x and y are 1.
C = xy
2. S is 1 only if the input variables x and y are not equal
S =x’y+xy’ = x XOR y
Addition of Multi-bit binary numbers

• At every bit position (stage) we need to add 3 bits.

• 1 bit for number A
• 1 bit for number B
• 1 carry bit coming from the previous stage
Full-Adder
A full adder is a combinational circuit that forms the arithmetic sum of three input
bits.
An arithmetic circuit that adds two bits( A, B) and a carry bit (Cin) and outputs a
sum bit (S) and a carry bit Cout.
• Full adder has an input carry while half adder does not.
Logic Symbol
Subtractors
● Subtraction -2 ways
○ Add complement of subtrahend with minuend – Can be implemented with full adders
○ Implement subtraction with logic circuits in a direct manner.
● In direct method each subtrahend bit of the number is subtracted from its
corresponding significant minuend bit to form a difference bit.
● If the minuend bit is smaller than the subtrahend bit, a 1 is borrowed from the
next significant position.
● A ‘1’, that has been borrowed must be conveyed to the next higher pair of bits
by means of a binary signal coming out of a given stage and going into the
next higher stage.
● Two types of subtractors- Half subtractor and full subtractor.
Half Subtractor
● A half-subtractor is a combinational circuit that subtracts two bits and
produces their difference.
● It also has an output to specify if a 1 has been borrowed.
● Designate the minuend bit by x and the subtrahend bit by y.
● To perform x-y, check the relative magnitudes of x and y. If x >=y(0-0,1-0,1-1)
no need to acquire a borrow. If x < y, (0-1), it is necessary to borrow a 1 from
the next higher stage.
● D = x’y+xy’
● B = x’y
Full Subtractor
● A full subtractor is a combinational circuit that performs a subtraction between
two bits taking into account that a 1 may have been borrowed by a lower
significant stage.
● The circuit has three inputs and two outputs.
● The three inputs x,y,z denote the minuend, subtrahend and previous borrow,
respectively.
● The two outputs, D and B, represent the difference and output borrow,
respectively .
● Questions:
1. Implement a full-subtractor with two half subtractors and an OR gate.
2. Design a combinational circuit that accepts a three-bit number and generates
an output binary number equal to the square of the input number.
● D = x’y’z+x’yz’+xy’z’+ xyz
z (x y)

B = x’y’z+x’yz’+x’yz+xyz
= z(xy+x’y’) +x’y(z+z’)
= z ( x xnor y) +x’y
Code Conversion
● To convert a binary code A to a binary code B, the input lines must supply the
bit combination of elements as specified by code A and the output lines must
generate the corresponding bit combination of code B.
● A combinational circuit performs this transformation by means of logic gates.
● Eg. of code converter BCD to excess 3.
Binary Parallel Adder
● A full adder can be used to add 3 bits.(2 bits and a previous carry).
● Consider the addition of two 4 bit numbers.
● When a pair of bits are added through a full adder, the circuit produces a carry to be
used with the pair of bits one significant position higher.
● The bits are added with full adders, starting from the least significant position to form
the sum bit and carry bit.
● The input carry Ci in the least significant position must be zero.
● The value of Ci+1 in a given significant position is the output carry of a full adder. This
value is transferred into the input carry of the full-adder that adds the bits one higher
significant position to the left.
● A binary parallel adder is a digital function that produces the arithmetic sum of two
binary numbers in parallel. It consists of full-adders connected in cascade, with the
output carry from one full adder connected to the input carry of the next full-adder.
● An n-bit parallel adder requires n full adders.
N-Bit Parallel Adder
● The full adder is capable of adding two single digit binary numbers along with
a carry input.
● But in practice we need to add binary numbers which are much longer than
one bit.
● To add two n-bit binary numbers we need to use the n-bit parallel adder.
● It uses a number of full adders in cascade.
● The carry output of the previous full adder is connected to the carry input of
the next full adder..
IC 7483 4 – Bit Binary Parallel Adder

A3 B 3 A2 B 2 A1 B 1 A0 B0

FA-3 FA-2 FA-1 FA-0

C0 C in

S 3 S 2 S1 S 0

Called Ripple Carry Adder

IC 7483 4 – Bit Binary Parallel Adder

A Binary number B Binary number

B 3 B 2 B1 B 0
A 3 A 2A1 A 0

IC 7483
Cin
C0
Carry
Carry Input
Output

S 3 S 2 S1 S 0

Sum
Output
Design of BCD Adder

● Adds two BCD numbers generate a valid result

● Points to note:
○ If sum≤9 or carry =0, No correction needed
○ If sum≥9 or carry =1, requires correction
○ Correction: add 0110 to the result
Design of BCD Adder
Block A BCD no. B BCD no.

Diagram:
C0 IC
7483-I S 3 S 2 S1 S 0
Ci
n

Logic
Circuit

Add 0110
Command

IC 7483-II
C0 Ci
n
S 3 S 2 S1 S 0
Design of BCD Adder

As we know BCD addition rules, we understand

that the 4 bit BCD adder should consists of
following:
 A 4 bit binary adder to add the given
two (4 bit numbers).
 A combinational logic circuit to check if sum is
greater than 9 or carry 1.
 One more 4 bit binary adder to add 0110 to the
invalid BCD sum or if carry is 1
BCD Adder
Logic Table for design of Logic circuit:
BCD Adder

● The correction is needed

○ when binary sum has o/p carry K=1
○ when Z8=1 (other 6 combinations)
■ Other than binary 1000 and 1001 which has 1 in Z 8
but both Z4 and Z2 are 0
■ So either Z4 or Z2 should have 1
● So the condition for correction can be derived as

C=K+Z8Z4+Z8Z2
When C=1, add 0110 to the sum generated
Design of BCD Adder
LOOK AHEAD CARRY ADDER/
CARRY LOOK AHEAD ADDER
 Limitation of ripple carry adder
● Each adder block waits for the carry to arrive from its
previous block. So, it is not possible to generate the
sum and carry of any block until the input carry is
known. The ith block waits for the (i-1)th block to produce
its carry.
● There will be a considerable time delay which is carry
propagation delay.
● The propagation time is equal to the propagation delay
of each adder block, multiplied by the number of adder
blocks in the circuit.

59
Full adder Unit
Look ahead carry adder
● Increase the speed of processing by predicting the
carry.

(AB).C-IN

A.B

C-Out = A.B+(AB).C-IN

Carry generator Carry propagator

(G) (P)

C-Out=G+P.C-IN
Code converter –Binary to gray code
g0 g1
g2 g3
b0
b1
b2
b3
Magnitude comparator
● It is a combinational circuit that compares two digital or binary numbers in order to
find out whether one binary number is equal, less than or greater than the other
binary number.
● Two inputs one for A and other for B and have three output terminals, one for A > B
condition, one for A = B condition and one for A < B condition.
1-Bit Magnitude Comparator
● A comparator used to compare two bits is called a single bit comparator. It
consists of two inputs each for two single bit numbers and three outputs to
generate less than, equal to and greater than between two binary numbers.

● The truth table for a 1-bit comparator is given below:

● A>B: AB'
● A<B: A'B
● A=B: A'B' + AB
2-Bit Magnitude Comparator
4-Bit Magnitude Comparator
● A comparator used to compare two binary numbers each of four bits is called a
4-bit magnitude comparator. It consists of eight inputs each for two four bit
numbers and three outputs to generate less than, equal to and greater than
between two binary numbers.

● In a 4-bit comparator the condition of A>B can be possible in the following four
cases:
If A3 = 1 and B3 = 0
If A3 = B3 and A2 = 1 and B2 = 0
If A3 = B3, A2 = B2 and A1 = 1 and B1 = 0
If A3 = B3, A2 = B2, A1 = B1 and A0 = 1 and B0 = 0
● Similarly the condition for A<B can be possible in the following four cases:
If A3 = 0 and B3 = 1
If A3 = B3 and A2 = 0 and B2 = 1
If A3 = B3, A2 = B2 and A1 = 0 and B1 = 1
If A3 = B3, A2 = B2, A1 = B1 and A0 = 0 and B0 = 1

The condition of A=B is possible only when all the individual bits of one number
exactly coincide with corresponding bits of another number.
4 bit magnitude comparator Ref:

● Consider two numbers A and B

● Equality of two bits can be expressed as

● For equality of two numbers all bits in the numbers

should be equal
○ Ie
DECODERS
● Decoders are combinational circuits that convert binary information from 'n'
coded inputs to a maximum of 2n unique outputs.
● Only one o/p will be activated for a particular combination of input.
● Decoder identifies and recognizes a particular code.
● In case the 'n' bit decoded information has unused bit combinations, the
decoder may have less than 2n outputs.
● eg: 2-to-4 decoder, 3-to-8 decoder or 4-to-16 decoder are other examples.
3-8 DECODER
● The number of available inputs are 3 and outputs are 8.
● Let us represent the inputs and outputs by symbol letters. Let us represent
the inputs by x, y, and z; and the outputs by D0, D1, D2, … D7.
BCD to decimal decoder
Combination logic implementation using decoder
● Any combinational circuit with n inputs and m outputs can be implemented
with an n-to-2n line decoder and m OR gates.
● Implement a full adder circuit with a decoder and two OR gates
Encoder
● An encoder is digital function that produces a reverse operation from that of a
decoder.
● An encoder has 2n input lines and n output lines.
● The output lines generate the binary code for the 2n input variables.
● Example: Octal to binary encoder.
● Octal to binary encoder consists of eight inputs, one for each of the eight
digits, and three outputs that generate the corresponding binary number.
● It is constructed with OR gates whose outputs can be determined from the
truth table given below
Priority Encoder
● This is a special type of encoder.
● Priorities are given to the input lines.
● If two or more input lines are “1” at the same time, then the input line with
highest priority will be considered.

● We considered one more output, V in order to know, whether the code available
at outputs is valid or not.
○ If at least one input of the encoder is ‘1’, then the code available at outputs is a valid one. In this
case, the output, V will be equal to 1.

○ If all the inputs of encoder are ‘0’, then the code available at outputs is not a valid one. In this
case, the output, V will be equal to 0.
PRIORITY ENCODER

● Special encoder – i/p s are given priority

INPUT OUTPUT
D0 D1 D2 D3 A B V
0 0 0 0 X X 0
1 0 0 0 0 0 1
X 1 0 0 0 1 1
X X 1 0 1 0 1
X X X 1 1 1 1 A = D2+D3
B = D3+D1
V=D3+D2+D1+D0
Multiplexer
● A multiplexer is a combinational circuit that selects binary information from
one of many input lines and directs it to a single output line.
● The selection of a single input line is controlled by a set of selection lines.
● There are 2n input lines and n selection lines whose bit combinations
determine which input is selected.
Advantages of Multiplexers

It reduces the number of wires.

So it reduces the circuit complexity

and cost.
We can implement many
combinational circuits using Mux.
It simplifies the logic design.

It does not need the k-map and

simplification.
Applications of Multiplexers

 It is used as a data selector to select one out of

many data inputs.

 It is used for simplification of logic design.

 It is used in data acquisition system.

 In designing the combinational circuits.

 In D to A converters.

 To minimize the number of connections.

Types of Multiplexers

2:1 Multiplexer

4:1 Multiplexer

8:1 Multiplexer

16:1 Multiplexer

32:1 Multiplexer

64:1 Multiplexer

and so
on…………
2:1 Multiplexer

Block
Diagram

Truth Table
Realization of 2:1 Mux using gates
4:1 Multiplexer
Realization of 4:1 Mux using gates
8:1 Multiplexer
 16:1 MULTIPLEXER

Enable Select Lines Output

E S3 S2 S1 S0 Y
0 X X X X 0
1 0 0 0 0 D0
1 0 0 0 1 D1
1 0 0 1 0 D2
1 0 0 1 1 D3
1 0 1 0 0 D4
1 0 1 0 1 D5
1 0 1 1 0 D6
1 0 1 1 1 D7
1 1 0 0 0 D8
1 1 0 0 1 D9
1 1 0 1 0 D10
1 1 0 1 1 D11
1 1 1 0 0 D12
Mux Tree

 The multiplexers having more number of inputs

can be obtained by cascading two or more
multiplexers with less number of inputs. This is
called as Multiplexer Tree.
 For example, 32:1 mux can be realized using
two 16:1 mux
8:1 Multiplexer using 4:1 Multiplexer
8:1 MUX using 4:1 MUX and a 2:1 MUX
16:1 Multiplexer using 8:1 Multiplexer
Realization of Boolean expression using Mux
 Combinational ckt Using MUX

Example 1:

Implement following Boolean expression using multiplexer

f ( A, B, C ) = m(0, 3, 5, 6)

 Since there are three variables, therefore a

multiplexer with three select input is required
i.e. 8:1 multiplexer is required
 The 8:1 multiplexer is configured as below to implement
given Boolean expression
Combinational ckt Using MUX
Combinational ckt Using MUX

Example 2
Combinational ckt Using MUX
Implement any Boolean function of ‘n’ variables with
a 2n-1 :1 MUX
● Express the function in sum of minterms.
● Let the ordered sequence of variables chosen for the minterm is ABCD..,where
A is the leftmost variable and BCD…, are the remaining n-1 variables.
● Connect the n-1 variables to the selection lines of the MUX with B connected to
the high-order selection line,C to the next high –order and so on down to the
last variable, which is connected to the s0.
● Since A is in the highest-order position in the sequence of variables, it will be
complemented in first half in the list of minterms, and uncomplemented in the
second half.
● List the inputs of the MUX and under them list all the minterms in two rows.
○ The first row list all those minterms where A is complemented, and the second row all the minterms with A
uncomplemented.
● Circle all the minterms of the function and inspect each column separately.
○ If the two minterms in a column are not circled, apply 0 to the corresponding multiplexer input.
○ If the two minterms are circled aply 1 to the corresponding multiplexer input.
○ If the bottom minterm is circled ant the top is not circled , apply A to the corresponding multiplexer input.
○ If the top minterm is circled ant the bottom is not circled , apply A’ to the corresponding multiplexer input.

● NB:It is not necessary to choose the leftmost variable in the ordered sequence of
variable list for the inputs to the multiplexer, we can choose any one of the variable as
input to the multiplexer.
● Eg:F(A,B,C) =∑(1,3,5,6)
De-multiplexer
Block Diagram of De-multiplexer
Types of De-multiplexers
1: 2 De-multiplexer
1:2 De-mux using basic gates
1: 4 De-multiplexer
1:4 De-mux using basic gates
1: 8 De-multiplexer
1: 8 De-multiplexer
1: 16 De-multiplexer
2:4 Decoder
2X4 DECODER WITH ENABLE ACTIVE LOW
4x16 decoder using 3x8 decoders
Parity Generator/Checker
● Even Parity Generator
● Circuit diagram of odd parity generator
● Even Parity Checker
● Odd Parity Checker

● NB: Refer section 4-9 in your textbook for parity generator/checker

(Pages:145-149)