Sequential logic circuits

(flipflops)

Mrs. M.S. Ranade

HOD Computer Engineering Department
 Classification of digital circuits
Digital circuits are classified into two categories
• Combinational logic circuits
• Sequential logic circuits

Parameter Combinational logic Sequential logic

circuits circuits
Output at any instant Present inputs Present inputs and past
depends on history of inputs
Memory Not required Required

Clock input Not required Required

Examples Adders, multiplexers, Flip-flops, registers,

decoders etc counters etc
 Sequential circuits

• In sequential logic circuits output is dependent on present

inputs and past history of these inputs
• Past history of inputs is provided by memory element
• A sequential circuit consists of a combinational circuit and a
memory element in a feedback path
• One bit of information is stored in memory element
• Contents of memory element can be changed by output of a
combinational circuit
 Clock signal

• Clock signal is a timing signal applied to the

sequential circuit
• It is a square wave signal
• Overall action of a flip flop is coordinated by a
clock signal
 Clock signal continued
• Depending upon triggering methods flip flops are
divided into two types
 Level triggered flip flops : sensitive to level of the
clock pulse
 Edge triggered flip flops : sensitive to transition of
the clock pulse
 Level triggered flip flops are of two types
 High level triggered
 Low level triggered
 Edge triggered flip flops are of two types
 Positive edge triggered
 Negative edge triggered
 One bit memory cell
• Basic digital memory circuit is known as flipflop
• It is capable of storing binary information
• It has two stable states, state 1 & state 0
• It can be obtained by using two NAND gates or two
NOR gates
 One bit memory cell continued

• One bit memory cell consists of two inverters G1 & G2

• Output of G1 is connected to input of G2
• Output of G2 is connected to input of G1
• Assume output of G1 = 1
• It is connected to input of G2, therefore output of G2 = 0
• This makes Q = 1 which confirms our assumption
• Similarly if Q = 0, then Q’ = 1, this is also consistent
with the circuit connection
 One bit memory cell continued
In the circuit shown
1. Outputs Q & Q’ are complementary
2. The circuit has two stable states Q = 0 (Reset) and Q
= 1 (Set)
3. The circuit continues to remain in any one state
This property of the circuit is referred as memory
RS Flipflop

• This RS flipflop is designed using 4

NAND gates G1, G2, G3, G4
• It has two inputs S & R and two
outputs Q & Q’
• Initially assume that Q = 1 and Q’ = 0
 RS Flipflop continued
1. If S = R = 0 outputs of G3 & G4 are 1, therefore inputs to G2
are 1&1, hence output Q’ = 0. inputs to G1 are 1 & 0, therefore
output Q = 1 i. e. output Q remains unchanged
2. If S = 0 & R = 1, output of G3 = 0 & output of G4 = 1,
therefore output Q’ = 1, inputs to G1 are now 1 & 1, output Q
= 0 i. e. flipflop is in reset state
3. If S = 1 & R = 0, outputs of G3 & G4 are 0 & 1 respectively,
therefore output Q = 1 and Q’ = 0. This is referred as set state
of the flipflop
4. If S = R = 1 both outputs Q & Q’ try to become 1 at a time
which is not allowed, therefore this input condition is
prohibited or it is known as forbidden state
Clocked RS Flipflop

• If RS flipflop is required to be set or reset in

synchronism with the clock, then the flip flop is
called as clocked RS flipflop
• In this circuit if the clock is present (logic 1), its
operation is exactly same as RS flipflop
• When the clock is absent (logic 0) gates G3 &
G4 are disabled i. e. the circuit responds to S &
R inputs only when clock is present
Preset & Clear inputs
• When power is switched on, output state of
the flipflop may be uncertain
• In many applications it is necessary to set or
reset the flipflop initially
• It can be achieved by using direct
(asynchronous) inputs preset & clear
• These inputs can be applied at any time
• When Pr = 0 & Cl = 1 flipflop will set i. e. Q
=1
• When Pr = 1 & Cl = 0 flipflop will reset i. e.
Q=0
• Once the state of flipflop is established
externally, these inputs sre connected to
logic 1
 Delay Flipflop ( D flipflop)

• In D flipflop S & R inputs are connected to each other through

NAND inverter i. e. flipflop has only one input D
• Hence S = R = 0 & S = R = 1 these two input conditions will be
avoided
• When clock = 0 flipflop will be disabled
• When clock = 1, NAND gates 3 & 4 will be enabled and Q will
be forced to equal the value of D i.e. if D = 0, Q = 0 & if D = 1,
Q=1
D flipflop continued
• When clock again becomes 0,
Q stores last value of D
• Input data appears at output of
D flipflop at the end of clock
pulse i. e. transfer of data from
input to output is delayed hence
the name delay/D flipflop
• D flipflops are used as delay
elements or they are used in
digital latches
Level triggered & edge triggered
flipflops
• Latch is a level
sensitive
• As long as clock is
active, latch output
keeps on changing
according to
changes in input
signal
• Flipflop is edge
sensitive
 JK flipflop

• Uncertainty in the state of RS flipflop when S = R = 1 can be

eliminated by converting it to JK flipflop
• Here outputs Q & Q’ are connected back to inputs of NAND
gates 4 & 3 respectively
• One way to build JK flipflop is as shown
 JK flipflop continued

1. When clock = 0 both NAND gates 3 & 4 will be disabled,

there is no change in output state
2. When clock = 1 & J = K = 0, NAND gates 3 & 4 will be
disabled, S’ = R’ = 1,therefore output Q retains its last
value
3. When J = 0 & K = 1, if Q = 1 then NAND gate 4 will give
output 0 i. e. R’ = 0 & S’ = 1,hence flipflop will reset on
the application of the clock
 JK flipflop continued
4. When J = 1 & K = 0, if Q = 0 then NAND gate 4 will
give output 1 & output of NAND gate 3 will be 0,hence
the flipflop will set
5. When J = K = 1 & if Q = 0,then output of NAND gate 4
will be 1 i. e. R’ = 1 & S’ = 0, therefore the flipflop will
set. On the other hand if J = K = 1 & if Q = 1 then
output of NAND gate 4 will be 0 i.e. R’ = 0 & S’ = 1,
therefore the flipflop will reset
Thus when J = K = 1 flipflop switches to opposite state i. e.
it toggles on the clock pulse
Toggle flipflop (T flipflop)

• J & K terminals of JK flipflop

are connected together to obtain
Toggle (T) flipflop
• It has only one input named T
• When T = 1, the flipflop toggles
on the application of every clock
pulse
• T flipflop divides the clock
frequency by 2
 Race around condition

• To overcome the drawback of RS flipflop feedback

connections are used in JK flipflop
• Here it is assumed that inputs do not change when clock = 1
• But because of the feedback connections. e. g. if J = k = 1,
Q = 0 & a clock pulse is applied at clock input
• After interval Δt output will change to Q = 1. now we have
J = K = 1 & Q = 1, therefore after another time interval Δt
output will again change to Q = 0
 Race around condition continued
• Hence we can say that during tON output of flipflop
will oscillate between 0 &1 and at the end of the
clock pulse output will be uncertain
• This situation is known as race around condition
• It can be avoided if tON < Δt < T in level triggered
flipflops but it is difficult as Δt is very small
• hence master slave flipflop is used to overcome this
difficulty or
• it can be overcome by using edge triggered flipflops
 Master Slave flipflop

• Master slave JK flipflop consists of two flipflops, one clocked

JK flipflop and other clocked RS flipflop
• JK flipflop acts as a master flipflop and RS flipflop acts as slave
flipflop
• Master is positive/high level triggered and slave is negative/low
level triggered as inverter is present in the clock line of slave
 Master Slave flipflop continued
• Master is active when clock = 1 & slave is inactive
• When clock = 0 master is inactive & slave is active
• When J = K = 1 & clock = 1, master is active, therefore output
of master will toggle, S & R inputs will also change, but as
slave is inactive outputs Q & Q’ will remain unchanged
• When J = K = 1 & clock = 1, master is active, therefore output
of master will toggle, S & R inputs will also change, but as
slave is inactive outputs Q & Q’ will remain unchanged
• When clock = 0, master is inactive & slave is active, therefore
output of slave will change, these changed outputs are returned
back to master inputs but as clock is 0, master is inactive
hence its outputs will not change
• This avoids race around condition as multiple toggling of
output is avoided
 Applications of flipflops

• Bounce elimination switch

• As memory element
• In registers
• In counters/timers
• As delay element
 Excitation table of a flipflop
• Truth table of a flipflop is also known as characteristic
table. It defines behaviour of the flipflop
• While designing sequential circuits, present state and next
state of the circuit are given and we have to find
corresponding input condition
• Present state and next state are states of the circuit prior to
and after clock pulse respectively
• Excitation table is useful for this purpose. It shows what
input is necessary to generate a given output
• Excitation table can be obtained from truth table of the
flipflop
Excitation table of RS & D flipflop
S R Qn+1 Present state Next state S R
0 0 Qn 0 0 0 X
0 1 0 0 1 1 0
1 0 1 1 0 0 1
1 1 Prohibited 1 1 X 0

Truth table of RS FF Excitation table of RS FF

Present state Next state D

D Qn+1 0 0 0
0 0 0 1 1
1 1 1 0 0
1 1 1

Truth table of D FF Excitation table of D FF

Excitation table of JK & T flipflop
J K Qn+1 Present state Next state J K
0 0 Qn 0 0 0 X
0 1 0 0 1 1 X
1 0 1 1 0 X 1
1 1 Qn’ 1 1 X 0

Truth table of JK Excitation table of JK FF

FF
Present state Next state T
T Qn+1 0 0 0
0 Qn 0 1 1
1 Qn’ 1 0 1
1 1 0

Truth table of T FF Excitation table of T FF

 IC 7474

•IC 7474 is 14 pin, dual positive edge triggered D flipflop

•Each D flipflop is with individual D, clock, set & reset inputs and
complementary outputs
•Set, reset inputs are asynchronous active low inputs
 IC 7474 continued

Operating mode Inputs Outputs

SD’ RD’ CP D Q Q’
Asynchronous set 0 1 X X 1 0
Asynchronous reset 1 0 X X 0 1
Set 1 1 1 1 0
Reset 1 1 0 0 1
 IC 7475

Inputs Outputs
E D Q Q’
1 0 0 1
• Q0 is level of Q before high to 1 1 1 0
low transition of E 0 X Q0 Q0’
 IC 7475 continued

•IC 7475 is 16 pin, 4 bit bistable latch used for

temporary storage of binary information
•IC provides complementary outputs Q & Q’
•Information applied at D input is transferred to Q
output when enable input is high
•When enable is low, last information will be available
at Q