TIMING ISSUES

IN DIGITAL CIRCUITS
MODULE – 2 PART - 2
INTRODUCTION

• In sequential circuits, correct operation depends on the precise ordering of switching

events, as incorrect timing can result in data corruption and functional failure.
• A well-established approach to ensure proper timing in such systems is the synchronous
design methodology, where all memory elements are updated simultaneously using a
globally distributed periodic clock signal..
• However, for synchronous systems to function reliably, strict constraints must be enforced
on the clock's generation and distribution to the various memory elements spread across
the chip.
• Two critical issues can arise in synchronous systems:
• Clock skew, which refers to the spatial variation in the arrival times of the clock
signal across different parts of the system, leading to potential timing mismatches.
• Clock jitter, which involves temporal variations in the clock period, introducing
uncertainty in event timings and impacting system stability.These variations
fundamentally limit the performance of synchronous designs, as excessive skew or
jitter can lead to malfunctions.
• An alternative approach is asynchronous design, which eliminates the need for a
global clock.
• In asynchronous systems, different components operate independently and
synchronize with each other using handshaking protocols.
• While this approach avoids clock-related issues, it comes with its own overhead in
terms of complexity and coordination delays.
• A key challenge in digital systems is synchronization between different clock
domains or when interfacing with asynchronous components.
• Specialized circuits are required to ensure data is transferred reliably across these
domains, avoiding metastability and data corruption.
• The chapter also introduces on-chip clock generation using feedback loops,
highlighting the advancements in clock distribution techniques that aim to improve
clock stability and accuracy, which are essential for maintaining performance in
high-speed circuits.
• This discussion addresses the trends and challenges in timing methodologies, with a
focus on both synchronous and asynchronous design approaches.
 Classification of Digital System
• In digital systems, signals are classified based on their relationship to a local clock.
• Signals that change only at specific, predetermined times can be categorized as
• synchronous,
• mesochronous, or
• plesiochronous relative to the system clock.
• A signal that changes at any arbitrary time, without following the clock, is considered
asynchronous.
 • A synchronous signal operates at the same frequency as the
Synchronous Interconnect local clock and has a known, fixed phase offset.
• In this timing method, the signal is aligned or "synchronized"
with the clock, allowing data to be sampled without
uncertainty.
• In digital logic design, synchronous systems are the simplest to
implement because data flows through the circuit in lockstep
with the clock.
• For example, the input signal (In) is first sampled by a register
(R1) to produce a signal (Cin) that is synchronized with the
system clock. This signal is then passed through a
combinational logic block.
• After a certain settling time, the output signal (Cout) becomes valid and is sampled by another register (R2)
to synchronize it with the clock.
• The "certainty period" of Cout refers to the time during which the data is valid, and this period is aligned
with the clock, allowing R2 to sample it reliably.
• The "uncertainty period" refers to the time when the data is not valid.
• This period limits how fast the system can operate, as the clock speed cannot exceed the time it takes for the
signals to stabilize.
Mesochronous interconnect • A mesochronous signal operates at the same frequency as the local
clock but has an unknown phase offset.
• This means that while both systems run at the same speed, the
signals are not perfectly aligned in time.
• This situation often occurs when data is transferred between two
different clock domains, where the transmitted data signal from
the first module has an unknown timing relationship with the clock
of the receiving module.
• In such cases, directly sampling the incoming data at the receiving
module isn't possible due to the phase uncertainty.
• To solve this, a mesochronous synchronizer is used to align the
data signal with the receiving clock, ensuring proper sampling.

• For example, consider two clock domains: ClkA and ClkB.

• The data signal D1 is synchronous with ClkA, but when transferred to the receiving module, it becomes
mesochronous with ClkB due to the unknown phase difference between ClkA and ClkB, as well as potential
interconnect delays.
• The synchronizer's job is to introduce a variable delay to the signal, ensuring that the delayed signal (D3) is correctly
aligned with ClkB.
• This phase adjustment is done by measuring the phase difference between the incoming signal and the local clock.
• Once the data is correctly aligned, register R2 can sample the incoming data during the certainty period, making the
output signal (D4) fully synchronous with ClkB.
Plesiochronous Interconnect
• A plesiochronous signal refers to one that has almost the same frequency as the local
clock but with a slight difference.
• This small frequency difference causes the phase relationship between the two
clocks to gradually drift over time.
• This scenario often arises when two interacting modules have independent clocks
generated from separate crystal oscillators, leading to frequency mismatches.
• In this situation, the signal transmitted by the originating module arrives at the
receiving module at a slightly different rate than the local clock.
• To handle this, a buffering scheme is used to ensure that all data is received properly.
• This type of interconnection, called plesiochronous interconnect, is usually found in
distributed systems, such as long-distance communication networks.
• In chip or board-level circuits, a common oscillator is often used to derive clocks,
which prevents such frequency mismatches.
• The provided diagram shows a possible framework for plesiochronous interconnect.
• The originating module sends data at an unknown rate characterized by clock C1, which is
plesiochronous with respect to the receiving module's clock C2.
• To manage this, a timing recovery unit derives a third clock (C3) from the incoming data sequence.
• The incoming data is buffered in a FIFO (First-In-First-Out) memory unit, where C3 is
synchronized with the data at the input of the FIFO and mesochronous with C1.
• Since the clocks from the originating and receiving modules are not perfectly matched, the system
might experience situations where:Data may be dropped if the transmission rate (C1) is faster than
the reception rate (C2).
• Data may be duplicated if the transmission rate is slower than the reception rate.
• To prevent issues, the FIFO must be large enough to accommodate these variations.
• The system can also be reset periodically to avoid overflow conditions, ensuring reliable
communication.
Asynchronous Interconnect

• The blocks communicate by sending signals

back and forth to ensure data is transferred
correctly.
Handshaking Process:
• Completion Signal (DV): When a block
finishes processing data, it generates a DV
signal, indicating that its output data is valid
and ready to be transferred.
• Interconnect Circuit: The interconnect
manages the communication between the
• The diagram illustrates a system using blocks. It handles the exchange of Request
asynchronous signals with no central clock (Req) and Acknowledge (Ack) signals,
• the modules work independently and ensuring both blocks agree when data should be
communicate using a handshaking protocol transferred.
Asynchronous System: • Initialization Signal (I): Once the next block
receives valid data, it sends the I signal to start
• Each self-timed logic block processes data at
its processing.
its own pace, without waiting for a clock
signal.
• The system works asynchronously, meaning each block performs its computations as soon
as the data is available, rather than waiting for a clock pulse
• This design avoids problems like clock skew (where different parts of a circuit receive the
clock signal at slightly different times), but adds complexity because the handshaking
protocol requires extra communication steps
• Advantages:
• Blocks work at their native speed, meaning computations happen as soon as the data
is ready.
• It’s modular, meaning each block can operate independently
• Drawback:
• The handshaking process introduces communication overhead, which can slow down
performance compared to a synchronous system
• In essence, the diagram shows how different blocks communicate without a global clock
by using this handshaking protocol to ensure that data is transferred and processed
correctly
Synchronous Design — An In-depth Perspective
• Virtually all systems designed today use a periodic synchronization signal or clock
• The generation and distribution of a clock has a significant impact on performance
and power dissipation
• For a positive edge-triggered system, the rising edge of the clock is used to denote
the beginning and completion of a clock cycle
• In the ideal world, assuming the clock paths from a central distribution point to
each register are perfectly balanced, the phase of the clock (i.e., the position of the
clock edge relative to a reference) at various points in the system is going to be
exactly equal
• However, the clock is neither perfectly periodic nor perfectly simultaneous. This
results in performance degradation and/or circuit malfunction
• Fig shows the basic structure of a The following timing parameters
synchronous pipelined datapath characterize the timing of the
• In the ideal scenario, the clock at sequential circuit
registers 1 and 2 have the same clock • The contamination (minimum) delay tc-
q,cd, and maximum propagation delay of
period and transition at the exact same the register tc-q.
time • The set-up (tsu) and hold time (thold) for
the registers.
• The contamination delay tlogic,cd and
maximum delay tlogic of the combinational
logic.
• tclk1 and tclk2, corresponding to the
position of the rising edge of the clock
relative to a global reference
• t_clk1 and t_clk2: These represent the positions of the rising edges of the
clock relative to a reference.
• t_cq_cd: Contamination (minimum) delay of register R1.
• t_cq_pd: Maximum propagation delay of R1.
• t_logic_cd and t_logic_pd: Minimum and maximum delays through the
combinational logic
• t_su: Setup time of the register (how early data needs to be stable before
the clock’s rising edge)
• t_hold: Hold time of the register (how long data must remain stable after
the clock’s rising edge)
• Clock Period Constraints:
The minimum clock period required to avoid timing violations is:
𝑇>𝑡𝑐𝑞_𝑝𝑑+𝑡𝑙𝑜𝑔𝑖𝑐_𝑝𝑑+𝑡𝑠𝑢
This equation ensures that data can propagate from R1 through the logic and be set up at R2
before the next clock edge

• Hold Time Constraints:

The hold time of the destination register (R2) must be less than the minimum propagation delay
of the logic network:
𝑡ℎ𝑜𝑙𝑑<𝑡𝑐𝑞_𝑐𝑑+𝑡𝑙𝑜𝑔𝑖𝑐_𝑐𝑑
​This ensures that data doesn’t change too soon after the clock edge, violating the hold time.
Clock Skew
• The spatial variation in arrival time of a clock transition on an integrated circuit is
commonly referred to as clock skew
• The clock skew between two points i and j on a IC is given by δ (i,j) = ti - tj ,
where t i and t j are the position of the rising edge of the clock with respect to a
reference.

• The clock skew can be positive or negative depending upon the routing direction
and position of the clock source
• The timing diagram for the case with positive skew is shown
• the rising clock edge is delayed by a positive δ at the second register
• Clock skew is caused by static path-length mismatches in the clock load and by
definition skew is constant from cycle to cycle.
• if in one cycle CLK2 lagged CLK1 by δ, then on the next cycle it will lag it by the
same amount.
• clock skew does not result in clock period variation, but rather phase shift.
Clock skew on performance
• A new input In sampled by R1 at edge 1 will propagate
through the combinational logic and be sampled by R2 on
edge 4.
• If the clock skew is positive, the time available for signal to
propagate from R1 to R2 is increased by the skew δ
• The output of the combinational logic must be valid one set-
up time before the rising edge of CLK2 (point 4).
• The constraint on the minimum clock period can then be
derived as:
• The rising edge of CLK2 happens before the rising edge
of CLK1. On the rising edge of CLK1, a new input is
sampled by R1.
• The new sampled data propagates through the
combinational logic and is sampled by R2 on the rising
edge of CLK2, which corresponds to edge 4
• a negative skew directly impacts the performance of
sequential system.
• However, a negative skew implies that the system never
fails, since edge 2 happens before edge 1
 Propagation and Contamination Delay Estimation
An example of how to estimate propagation and contamination delays in a logic
circuit.
Propagation Delay: maximum time it takes for a change at the input of a circuit
to cause a change at the output. It represents the worst-case delay when signals
travel through the circuit.
2.Contamination Delay: minimum time before the output starts to change after
the input changes. It happens due to the fastest path through the circuit.

• The circuit has two main paths for signal travel: Path 0 and Path 1.
Path 0 goes through the logic gates labeled as AND1, AND2, and AND3.
Path 1 involves the gates OR1 and OR2.
• The contamination delay is always through the fastest path. In this circuit, that path goes through the gates OR1 and OR2, giving a
contamination delay of 2 * t_gate, where t_gate is the delay of a single gate.
• When analyzing the propagation delay, which looks for the slowest path, things get a bit tricky:
If inputs A and B have specific values (A = 1, B = 0), the signal travels through OR1 and OR2, resulting in a delay of 3 * t_gate.
If both A and B are equal to 1, the signal goes through the gates AND1, OR1, AND3, and OR2, resulting in a delay of 4 * t_gate.
• False Path
Path 0 is called a false path. This means that even though it seems like a possible path, the circuit conditions are such that it never
actually gets used. So, it's not considered in the worst-case propagation delay.
Clock Jitter

• Clock jitter refers to the temporal variation of the clock period at a given point —
that is, the clock period can reduce or expand on a cycle-by-cycle basis
• Jitter can be measured and cited in one of many ways.
• Cycle-to-cycle jitter refers to time vary of a single clock period and for a given spatial
location i is given as Tjitter,i(n) = Ti , n+1 - Ti,n - TCLK,

where Ti,n is the clock period for period n,

Ti , n+1 is clock period for period n+1, and

TCLK is the nominal clock period

Jitter directly impacts the performance of a sequential system

• The nominal clock period as well as variation in

period. Ideally the clock period starts at edge 2 and
ends at edge 5 and with a nominal clock period of
TCLK.
• However, as a result of jitter, the worst case scenario
happens when the leading edge of the current clock
period is delayed (edge 3), and the leading edge of the
next clock period occurs early (edge 4).
• As a result, the total time available to complete the
operation is reduced by 2 tjiiter in the worst case and is
given by

The above equation illustrates that jitter directly reduces the performance of a sequential
circuit. Care must be taken to reduce jitter in the clock network to maximize performance.