Computer Organization and

Assembly Language
CSC 325
Microprocessor/
Microcontroller Architecture
 Outline
 Introduction to MPU System
 Microprocessors and Microcontrollers
 Microprocessor Architecture
 Addressing Mode
 Address calculation
 Assembly Language Programming
Introduction
I/O Device 0 Data
Data
Code
Memory
Address
CPU
I/O Device 1 Data

Address
Data
I/O Device N Data
Memory
Data
Microprocessor Architecture
Addressing Mode
 Addressing Mode
 The term addressing modes refers to the way in which
the operand of an instruction is specified.
 Addressing modes of 8086
 Register
 Immediate
 Direct
 Register indirect
 Based relative
 Indexed relative
 Based indexed relative
Addressing Mode
 Register
 Involves the use of registers
 Memory is not accessed, so faster
 Source and destination registers must match in size.
 MOV BX,DX
 MOV ES,AX
 ADD AL,BH
 MOV AL,CX ;not possible
Addressing Mode
 Immediate
 Source operand is a constant
 Possible in all registers except segment and flag
registers.
 MOV BX,1234H ; move 1234H into BX
 MOV CX,223 ; load the hexadecimal value into CX
 ADD AL,40H ;
 MOV DS,1234H ;illegal
Addressing Mode
 Direct
 Address of the data in memory comes immediately
after the instruction operand is a constant
 The address is the offset address. The offset address
is put in a rectangular bracket
 MOV DL,[2400] ; move contents of DS:2400H into DL
Addressing Mode
 Find the physical address of the memory location and
its content after the execution of the following
operation. Assume DS=1512H
 MOV AL,99H
 MOV [3518],AL
 Physical address of DS:3518 => 15120+3518=18638H
 The memory location 18638H will contain the value 99H
Addressing Mode
 Register indirect
 The address of the memory location where the
operand resides is held by a register.
 SI, DI and BX registers are used as the pointers to
hold the offset addresses.
 They must be combined with DS to generate the 20-bit
physical address
 MOV AL,[BX] ; moves into AL the contents of the memory
location pointed to by DS:BX
 MOV CL,[SI] ; move contents of DS:SI into CL
 MOV [DI],AH ; move the contents of AH into DS:DI
Addressing Mode
 Based relative
 BX and BP are known as the base registers. In this
mode base registers as well as a displacement value
are used to calculate the effective address.
 The default segments used for the calculation of
Physical address (PA) are DS for BX, and SS for BP.
 MOV CX,[BX]+10 ; move DS:BX+10 and DS:BX+11 into CX ;
PA = DS (shifted left) +BX+10
 Note that, the content of the low address will go into CL and
the high address contents will go into CH.
 There are alternative coding:
 MOV CX,[BX+10], MOV CX,10[BX]
 BX+10 is effective address
Addressing Mode
 Indexed relative
 Indexed relative addressing mode works the same as
the based relative addressing mode.
 Except the registers DI and SI holds the offset
address.
 MOV DX,[SI]+5 ;PA=DS(shifted left)+SI+5
 MOV CL,[DI]+20 ;PA=DS(shifted left)+DI+20
Addressing Mode
 Based indexed relative
 The combination of the based and indexed addressing
modes.
 One base register and one index register are used.
 MOV CL,[BX][DI]+8 ;PA=DS(shifted left)+BX+DI+8
 MOV CH,[BX][SI]+20 ;PA=DS(shifted left)+BX+SI+20
 MOV AH,[BP][DI]+12 ;PA=SS(shifted left)+BP+DI+12
 MOV AL,[BP][SI]+29 ;PA=SS(shifted left)+BP+SI+29
 Alternative coding
 MOV CL,[BX+DI+8]
 MOV CL,[DI+BX+8]
Address calculation
 Physical Address
 The 20 bit address which we needs to be stored.
 It ranges from 00000H to FFFFFH (Hexadecimal
notation) .
 Base Address
 The address at which a given memory segment starts
and we use it for de-markation.
 Offset address
 (Distance from the base address) is a location with 64
kb segment range. It ranges from 0000H to FFFFH
Address calculation
 Logical address
 Something we denote on paper as a short hand
representation of the above addresses. It consists of a
segment value and offset address.
 Logical address is specified as Segment base : Offset
value.
Address calculation
 Physical address is obtained by shifting the
segment address 4 bits to left adding the offset
address.
 Physical address = ( Segment base*10H ) + Offset
Value.
 Logical address:A4FBH:4872H
 Segment's base address:A4FBH
 Offset value:4872H
 Shifting the segment address 4 bits to left A4FBH<<4 gives
A4FB0H
 Now adding offset address to A4FB0H
 A4FB0H+4872H=A9822H
Assembly Language
Programming
 Data Movement Instructions
 Arithmetic and Logic Instructions
 Program Control Instructions
 Special Instructions
 Assembly Language Version
 operation destination, source
 operation destination
 operation source
 operation
Assembly Language
Programming
 Data Movement Instructions

 ‘MOV’ transfers a constant, contents of memory or

register to a register or memory.
 MOV AX,DX Transfers contents of DX to AX, leaving DX unchanged
 MOV AL,CH Transfers contents of CH to AL, leaving CH unchanged
 MOV BL,CX Not allowed
 MOV AH,56 56 decimal is transferred to AH
 MOV BX,0ABCDH Transfers ABCD hexadecimal to BX
 MOV 67H,BL Not allowed
 MOV DS,3467H Not allowed
 MOV DS,BX Loads DS with contents of BX, leaving BX unchanged
 MOV [2345H],AH Transfers contents of AH to the memory location
whose offset is 2345H
 MOV [DI],56H Transfers 56H to the memory location whose offset is
stored in DI
 MOV [DI],[SI] Memory to memory move is not allowed
Assembly Language
Programming
 MOV Instructions

Destination Operand
MOV
Source General Segment Memory
Constant
Operand Register Register Location

General
Yes yes yes no
Register

Segment
Yes no yes no
Register

Memory
Yes yes no no
Location
Constant Yes no yes no
Instruction Set
1. Data Transfer Instructions

Instructions that are used to transfer data/ address in to

registers, memory locations and I/O ports.

Generally involve two operands: Source operand and

Destination operand of the same size.

Source: Register or a memory location or an immediate

data
Destination : Register or a memory location.

The size should be a either a byte or a word.

A 8-bit data can only be moved to 8-bit register/ memory

and a 16-bit data can be moved to 16-bit register/ memory.
Assembly Language
Programming
 Arithmetic Instructions
 ADD
 ADD instruction adds values exiting in two registers, register and
memory, immediate and memory, immediate and register. To add two
values existing in AL and BH register, ADD is used as:
 ADD AL, BH
 This instruction adds the contents of AL and BH registers, leaving
sum in AL and BH unchanged. ADD is applied, for example, on CX
and DX in the same way. Consider CX is containing 18 and DX
containing 25 before executing the following instruction.
 ADD CX, DX
 After this instruction is executed, CX is left with 43, DX with 25 and
CF with 0.
 Any 8-bit register (AH, AL, BH, BL, CH, CL, DH, DL) can be used
with ADD. For 16-bit addition, ADD can be applied on AX, BX, CX,
DX, SI and DI. You are encouraged to check the validity of ADD
instruction for other 16-bit registers yourself.
Assembly Language
Programming
 Arithmetic Instructions
 ADC
 ADC, pronounced as Add with Carry, instruction adds the content of
operands along with value in carry flag that exists in it at the instant
instruction ADC is executed. Consider SI contains 15678, DI contains
325 and CF is set. After executing following instruction,
 ADC SI, DI
 SI is left with 16004 (3E84H), DI with 325 (145H) and CF is cleared
as the latest result does not produce overflow condition.
Assembly Language
Programming
 Arithmetic Instructions
 INC
 Increment instruction INC adds 1 to the contents of its operand. It can
be applied on any 8-bit register (AH, AL, BH, BL, CH, CL, DH, DL).
For 16-bit increment, INC can be applied on AX, BX, CX, DX, SI and
DI. You are encouraged to check the validity of INC instruction for
other 16-bit registers yourself.
 Consider AL contains 97H before execution of following intrusion.
 INC AL
 After execution, AL is left with 98H.
Assembly Language
Programming
 Arithmetic Instructions
 SUB
 SUB instruction subtracts the contents of operand2 from operand1
and leaves the difference in operand1, with operand2 unchanged.
 SUB operand1, operand2

 Consider content of AH are to be subtracted from content of DL then

SUB can be used as,
 SUB DL, AH
 For 16-bit subtraction,
 SUB DX, DI
 SUB BX, AX
 Any 8-bit register (AH, AL, BH, BL, CH, CL, DH, DL) can be used
with SUB. For 16-bit subtraction, SUB can be applied on AX, BX, CX,
DX, SI and DI. You are encouraged to check the validity of SUB
instruction for other 16-bit registers yourself.
Assembly Language
Programming
 Arithmetic Instructions
 SBB
 SBB, pronounced as Subtract with Borrow, subtracts the contents of
operand2 and CF from the content of operand1 and leaves the result
in operand1. Operand2 is left unchanged and CF depends upon
whether most significant bit in operand1 required a borrow bit or not.
If borrow was required CF is set, otherwise cleared. Format of SBB
is,
 SBB operand1, operand2
 Consider CF is set, BX = 67ABH and DX = 100H before executing
following instruction.
 SBB BX, DX
 After execution, BX is left with 66AAH, DX with 100H and CF is
cleared.
Assembly Language
Programming
 Arithmetic Instructions
 DEC
 Decrement instruction DEC subtracts 1 from the contents of its
operand. It can be applied on any 8-bit register (AH, AL, BH, BL, CH,
CL, DH, DL). For 16-bit decrement, DEC can be applied on AX, BX,
CX, DX, SI and DI. You are encouraged to check the validity of DEC
instruction for other 16-bit registers yourself.
 Consider DI contains 55968 before execution of following intrusion.
 DEC DI ; after execution, DI is left with 55967.
Assembly Language
Programming
 Arithmetic Instructions
 NEG
 NEG instruction is single operand instruction that leaves the operand
with 2’s complement of its original data. For example register AX
contains 12656 (3170H). After executing NEG on AX, new contents
of AX will be CE90H which is -12656. NEG can be applied on 8-bit
registers, 16-bit registers or memory location. Consider,
 NEG AX
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
ADD reg2/ mem, reg1/mem

ADC reg2, reg1 (reg2)  (reg1) + (reg2)

ADC reg2, mem (reg2)  (reg2) + (mem)
ADC mem, reg1 (mem)  (mem)+(reg1)

ADD reg/mem, data

ADD reg, data (reg)  (reg)+ data

ADD mem, data (mem)  (mem)+data

ADD A, data

ADD AL, data8 (AL)  (AL) + data8

ADD AX, data16 (AX)  (AX) +data16
 8086

Instruction Set
Microprocessor

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
ADC reg2/ mem, reg1/mem

ADC reg2, reg1 (reg2)  (reg1) + (reg2)+CF

ADC reg2, mem (reg2)  (reg2) + (mem)+CF
ADC mem, reg1 (mem)  (mem)+(reg1)+CF

ADC reg/mem, data

ADC reg, data (reg)  (reg)+ data+CF

ADC mem, data (mem)  (mem)+data+CF

ADDC A, data

ADD AL, data8 (AL)  (AL) + data8+CF

ADD AX, data16 (AX)  (AX) +data16+CF
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
SUB reg2/ mem, reg1/mem

SUB reg2, reg1 (reg2)  (reg1) - (reg2)

SUB reg2, mem (reg2)  (reg2) - (mem)
SUB mem, reg1 (mem)  (mem) - (reg1)

SUB reg/mem, data

SUB reg, data (reg)  (reg) - data

SUB mem, data (mem)  (mem) - data

SUB A, data

SUB AL, data8 (AL)  (AL) - data8

SUB AX, data16 (AX)  (AX) - data16
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
SBB reg2/ mem, reg1/mem

SBB reg2, reg1 (reg2)  (reg1) - (reg2) - CF

SBB reg2, mem (reg2)  (reg2) - (mem)- CF
SBB mem, reg1 (mem)  (mem) - (reg1) –CF

SBB reg/mem, data

SBB reg, data (reg)  (reg) – data - CF

SBB mem, data (mem)  (mem) - data - CF

SBB A, data

SBB AL, data8 (AL)  (AL) - data8 - CF

SBB AX, data16 (AX)  (AX) - data16 - CF
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
INC reg/ mem

INC reg8 (reg8)  (reg8) + 1

INC reg16 (reg16)  (reg16) + 1

INC mem (mem)  (mem) + 1

DEC reg/ mem

DEC reg8 (reg8)  (reg8) - 1

DEC reg16 (reg16)  (reg16) - 1

DEC mem (mem)  (mem) - 1

Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
CMP reg2/mem, reg1/ mem

CMP reg2, reg1 Modify flags  (reg2) – (reg1)

If (reg2) > (reg1) then CF=0, ZF=0, SF=0

If (reg2) < (reg1) then CF=1, ZF=0, SF=1
If (reg2) = (reg1) then CF=0, ZF=1, SF=0

CMP reg2, mem Modify flags  (reg2) – (mem)

If (reg2) > (mem) then CF=0, ZF=0, SF=0

If (reg2) < (mem) then CF=1, ZF=0, SF=1
If (reg2) = (mem) then CF=0, ZF=1, SF=0

CMP mem, reg1 Modify flags  (mem) – (reg1)

If (mem) > (reg1) then CF=0, ZF=0, SF=0

If (mem) < (reg1) then CF=1, ZF=0, SF=1
If (mem) = (reg1) then CF=0, ZF=1, SF=0
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
CMP reg/mem, data

CMP reg, data Modify flags  (reg) – (data)

If (reg) > data then CF=0, ZF=0, SF=0

If (reg) < data then CF=1, ZF=0, SF=1
If (reg) = data then CF=0, ZF=1, SF=0

CMP mem, data Modify flags  (mem) – (mem)

If (mem) > data then CF=0, ZF=0, SF=0

If (mem) < data then CF=1, ZF=0, SF=1
If (mem) = data then CF=0, ZF=1, SF=0
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
CMP A, data

CMP AL, data8 Modify flags  (AL) – data8

If (AL) > data8 then CF=0, ZF=0, SF=0

If (AL) < data8 then CF=1, ZF=0, SF=1
If (AL) = data8 then CF=0, ZF=1, SF=0

CMP AX, data16 Modify flags  (AX) – data16

If (AX) > data16 then CF=0, ZF=0, SF=0

If (mem) < data16 then CF=1, ZF=0, SF=1
If (mem) = data16 then CF=0, ZF=1, SF=0
Assembly Language
Programming
 Logic Instructions
 NOT
 NOT instruction takes one complement of operand that can be 8-bit
data or 16-bit data. For example in order to apply NOT on AH
register, following syntax is used.
 NOT AH
 After executing this instruction, AH is left with complement of its
contents prior to execute this instruction.
 Any 8-bit register (AH, AL, BH, BL, CH, CL, DH, DL) can be used
with NOT. For 16-bit NOT, it can be applied on AX, BX, CX, DX, SI
and DI. You are encouraged to check the validity of SUB instruction
for other 16-bit registers yourself.
Assembly Language
Programming
 Logic Instructions
 AND
 AND instruction do logical AND on two 8-bit data or on two 16-bit
data. For example, in order to logically AND contents of BH and DL,
AND is used as:
 AND BH, DL
 This instruction logically ANDs the contents of BH and DL registers,
leaving result in BH and DL remains unchanged. AND can be applied
on 16-bit data stored in registers in the similar way. Any 8-bit register
(AH, AL, BH, BL, CH, CL, DH, DL) can be used with AND. For 16-bit
AND, instruction can be applied on AX, BX, CX, DX, SI and DI. You
are encouraged to check the validity of AND instruction for other 16-
bit registers yourself.
Assembly Language
Programming
 Logic Instructions
 OR
 OR instruction executes logical OR on two 8-bit data or on two 16-bit
data. For example, in order to logically OR contents of BH and DL,
OR is used as:
 OR BH, DL
 This instruction logically ORs the contents of BH and DL registers,
leaving result in BH and DL remains unchanged. OR can be applied
on 16-bit data stored in registers in the similar way. Any 8-bit register
(AH, AL, BH, BL, CH, CL, DH, DL) can be used with OR. For 16-bit
OR, instruction can be applied on AX, BX, CX, DX, SI and DI. You
are encouraged to check the validity of OR instruction for other 16-bit
registers yourself.
Assembly Language
Programming
 Logic Instructions
 XOR
 XOR instruction executes exclusive OR on two 8-bit data or on two
16-bit data. For example, in order to exclusive OR contents of BH
and DL, XOR is used as:
 XOR BH, DL
 This instruction XORs the contents of BH and DL registers, leaving
result in BH and DL remains unchanged. XOR can be applied on 16-
bit data stored in registers in the similar way. Any 8-bit register (AH,
AL, BH, BL, CH, CL, DH, DL) can be used with XOR. For 16-bit XOR,
instruction can be applied on AX, BX, CX, DX, SI and DI. You are
encouraged to check the validity of XOR instruction for other 16-bit
registers yourself.
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …