Branch & Call

Chapter 4

Dr. Umer Farooq Ahmed

 Topics
 Introduction to branch and call
 Branch
 Call
 LR
 Calling a function
 Time Delay

2
 Branch and Call
 CPU executes instructions
one after another.
 For example in the following 1 void main ()
2 {
C program, CPU first 3 a = b + c;
executes the instruction of 4 c -= 2;
line 3 (adds b and c), then 5 d = a + c;
executes the instruction of 6 }
line 4.

3
 Branch and Call (Continued)
 But sometimes we need the CPU to
execute, an instruction other than the next
instruction. For example:
 When we use a conditional instruction (if)
 When we make a loop
 When we call a function

4
 Branch and Call (Continued)
 Example 1: Not executing
the next instruction,
because of condition.
 In the following example, 1
2
void main ()
{
the instruction of line 6 is 3 int a = 2;

not executed. 4 int c = 3;

5 if (a == 8)
6 c = 6;
7 else
8 c = 7;
9 c = a + 3;
}

5
 Branch and Call (Continued)
 Example 2: In this
example the next
instruction will not be
executed because of 1 void main ()
2
loop.
{
3 int a, c = 0;
 In the following example, 4 for(a = 2; a < 4; a++)
5
the order of execution is
c += a;
6 a = c + 2;
as follows: 7 }

Line 4 8
9

Line 5

Again, line 4

Again line 5

Line 6

6
 Branch and Call (Continued)
 Example 3: Not executing
the next instruction,
because of calling a Code

function. 1 void func1 ();

2 void main ()
 In the following example, 3 {

the instruction of line 6 4 int a = 2, c = 3;

is not executed after line 5

6
func1 ();
c = a + 3;
5. 7 }
8 void func1 (){
9 int d = 5 / 2;
10 }
11

7
 Branch and Call (Continued)
 In the assembly language, there are 2
groups of instructions that make the CPU
execute an instruction other than the next
instruction. The instructions are:
 Branch: used for making loop and condition
 Call: used for making function calls

8
 Branch
 Branch changes the Program Counter
(PC) and causes the CPU to execute an
instruction other than the next
instruction.

9
 Branch in ARM
 There are 2 branch
instructions in ARM: B and
BX. Code
 We label the location where 1 MOV R1, #0
we want to jump, using a 2 MOV R2, #2

unique name 3 L1
L1 ADD R1, R1, R2
4 B L1
 Then, in front of the branch 5 SUB R10,R1,R5
instruction we mention the
name of the label.
 This causes the CPU to
jump to the location we
have labeled, instead of
executing the next
instruction.

10
 Ways of specifying the branch target
 B and BX provide the branch address using
2 different ways:
 B operand
 PC = PC + (operand*2)

 BX Rn
 PC = Rn register

11
 B (Branch)
 B PC = PC + (operand×2)
 To execute B: The operand shifts left and
then it is added to the current value of PC.

1110 0xxx XXXX XXXX

 Example:1110 0000 0000 0000 0000 0000 0000 0111


Operand = 000000000111

PC = PC + 000000001110

12
 B instruction

To execute B the operand shifts left and then it is added to the current value of PC.
 Cortex-M has a 3-stage pipeline. So, when an instruction is executed, PC points to 4 bytes below.

PC:0800001C
0800000C
08000010
0800001E
08000014 Addres Code
s
+ 800000 EXPORT __main
8
00000018 __main MOV R1,#0x15
Machine 800000
code: operand
opCode MOV R7, #5
8
E002 800000
B LBL_NAME
Shift left C MOV R8, #4
00000004
800001 ADD R8, R8, R7
0
8000018 LBL_NAME
Machine 800001
code: operand
opCode ADD R6, R6, R7
2
E7FD 800001
B LBL_NAME
FFFFFFFA 6
800001
8
800001
8
800001
A
800001
C 13
 BX
 BX Rn PC = Rn 0100 0111 0nnn n000

BX R3 0100 0111 0001 1000

 The Program counter is loaded
with the contents of Rn register.
 For example, if R5 points to

location 100, by executing BX

R5, the CPU jumps to location
100.

14
 BX instruction
 To execute BX:

The value of a register is loaded to the PC.

Addres Code
PC:0800000C
08000010
08000012 s
800000 AREA PROG,CODE,READONLY
8
__main MOV R1,#0x15
R7:00000000
80000016 800000
LDR R7, =LBL1
8
BX R7
800000
C MOV R8, #4
800000 ADD R8, R8, R7
E
8000016 LBL1
800001
ADD R6, R6, R7
0
B LBL1
800001
4
800001
6
800001
6
800001
8
800001
A 15
 Conditional Jump in ARM
D31 D30 D29 D28 ………. D7 D6 D5 D4 D3 D2 D1 D0
CPSR: N Z C V Reserved I F T M4 M3 M2 M1 M0

Negative oVerflow
Zero carry

 The conditional jump instructions in ARM are as follows:

Instruction Abbreviation of Action

BCS lbl branch if carry set Branch to location lbl if C = 1
BHS lbl branch if higher or
same
BCC lbl branch if carry clear Branch if C = 0
BLO lbl branch if lower
BEQ lbl branch if equal Branch if Z = 1
BNE lbl branch if not equal Branch if Z = 0
 The N and V flags are related to signed numbers and their
BLS lbl
branch branch ifare
instructions lower or Branch
discussed if Z = 15.or C = 0
in Chapter
same
16
 Conditional vs. Unconditional
There are 2 kinds of Branch
 Unconditional Branch: When CPU executes an
unconditional branch, it jumps unconditionally
(without checking any condition) to the target
location.

Example: BX and B instructions
 Conditional Branch: When CPU executes a
conditional branch, it checks a condition, if the
condition is true then it jumps to the target location;
otherwise, it executes the next instruction.

17
 Usages of Conditional jump
 Conditions
 Loop

18
 Conditions
 When b is subtracted from a:
 The result is zero, when a is equal to b a
 Carry will be set when a >= b -b

19
 Example 1
 Write a program that if R0 is equal to R1
then R2 increases.

 Solution: R0 == R1
No
SUBS R0,R0,R1 ;Z will be set if R0 == R1
BNE NEXT ;if Not Equal jump to next
Yes
ADD R2,R2,#1
NEXT increment R2

20
 Example 2
 Write a program that if R6 < R4 then R2
increases.

 Solution: R6 < R4
No

SUBS R6,R6,R4 ;C will be set when R6 >= R4

BCS L1 ;if Carry set jump to L1 Yes
ADD R2,R2,#1
L1 increment R2

21
 Example 3
 Write a program that if R6 >= R4 then R2
increases.

 Solution: R6 >= R4
No

SUBS R6,R6,R4 ;C will be set when R6 >= R4

BCC L1 Yes
;jump to L1 if Carry cleared
ADD R2,R2,#1
L1 increment R2

22
 Example 4: IF and ELSE
int main ( )
R7 = 5
{
R7 = 5;
if (R0 > R1)
R2++; No
R0 > R1
else
R2--;
R7++; Yes
}

increment R2

MOV R7,#5
SUBS R1,R1,R0 ;C is set when R1 >= R0 decrement R2

BCS ELSE_LABEL ;jump to else if set

ADD R2,R2,#1
JMP NEXT
ELSE_LABEL
SUB R2,R2,#1 increment R7

NEXT
ADD R7,R7,#1

23
 Loop
 Write a program that executes the
instruction “ADD R3,R3,R1” 9 times.
R6 = 9
 Solution:
MOV R6,#9 ;R6 = 9
R3 = R3 + R1
L1 ADD R3,R3,R1
SUBS R6,R6,#1 ;R6 = R6 - 1
BNE L1 ;if Z = 0
R6 = R6 - 1
L2 B L2 ;Wait here forever

Yes
R6 > 0

No

END

24
 Loop
 Write a program that calculates the result
of 9+8+7+…+1
R6 = 9
R7 = 0
 Solution:
R7 = R7 + R6
MOV R6, #9 @R6 =
9
MOV R7, #0 @R7 =
0
L1 ADD R7,R7,R6 @R7 =
R7 + R6 R6 = R6 - 1
SUBS R6,R6,#1 @R6 =
R6 - 1
BNE L1 @if Z = 0
L2 B L2 @Wait here forever
Yes
R6 > 0

No

END

25
 Loop
 Write a program that calculates the result
of 20+19+18+17+…+1
R6 = 20
 Solution: R7 = 0

MOV R6, #20 @R6 =

20 R7 = R7 + R6

MOV R7, #0 @R7 =

0
L1 ADD R7,R6,R6 @R7 =
R7 + R6
R6 = R6 - 1
SUBS R6,R6,#1 @R6 =
R6 - 1
BNE L1 @if Z = 0
L2 B L2 @Wait here forever
Yes
R6 > 0

No

END

26
 Loop
for (init; condition; calculation) init

{
do something Do something

} calculation

Yes
Condition

No

END

27
 Loop
 Write a program that calculates 1+3+5+…
+27
 Solution: R0 = 0
R6 = 1
MOV R0,#0
MOV R6,#1 R0 = R0 + R6

L1 ADD R0,R0,R6
ADD R6,R6,#2 ;R16 = R16 + 2 R6 = R6 + 2

SUBS R7,R6,#27
BCC L1 ;if R6 <= 27 jump L1
Yes
R6 <= 27

No

END

28
 CMP instruction
 CMP sets the flags the same way as SUBS.
But does not store the result of subtraction.
So, it suits for comparing.

MOV R0,#0 MOV R0,#0

MOV R6,#1 MOV R6,#1
L1 ADD R0,R0,R6 L1 ADD R0,R0,R6
ADD R6,R6,#2 ADD R6,R6,#2
SUBS R7,R6,#27 CMP R6,#27
BCC L1 BCC L1

29
Conditional Execution in ARM (Case Study)
31 28 27 26 0

Cond Instruction

Bits Mnemonic Extension Meaning Flag

0000 EQ Equal Z=1
0001 NE Not equal Z=0
0010 CS/HS Carry Set/Higher or Same C=1
0011 CC/LO Carry Clear/Lower C=0
0100 MI Minus/Negative N=1
0101 PL Plus N=0
0110 VS V Set (Overflow) V=1
0111 VC V Clear (No Overflow) V=0
1000 HI Higher C = 1 and Z = 0
mov r1,
r1,
1001
#10
HS
; r1 =Lower
10 or Same C = 1 and Z = 1
cmp r1, #0 ; compare r1 with 0
1010 GE Greater than or Equal N=V
addne r1, r1, #10 ; thisLess
line is executed if z = 0
1011 LT than N≠V
; (if in the last cmp operands were not equal)
1100 GT Greater than Z = 0 and N = V
1101 LE Less than or Equal Z = 0 or N ≠ V
1110 AL Always (unconditional)
1111 --- Not Valid

30
 Calling a Function
 To execute a call:
 Address of the next instruction is saved in LR (R14).
 PC is loaded with the subroutine address

Addres Code
s
08000010 AREA PROG,CODE,READONLY
08000010 __main MOV R1, #5
Machine MOV R2, #6
08000014
code:
F000F803 08000018 BL FUNC_NAME
Shiftoperan
opCod left 0800001C
0800001C MOV R2, #6
e d
0006 08000020 L1 B L1

LR: 0800001C
00000000 08000022 FUNC_NAME
08000022 ADD R2,R2,R1
08000024 SUB R2,R2,#3
PC:0800001C
08000014
08000028
08000024
0800002C
08000018 BX LR
08000028
+ 0800002A
08000022

31
 PROC and ENDP
 The directives are used to mark the
beginning and end of a subroutine:

FUNC_NAME PROC
...
BX LR
ENDP

32
Time delay

33
 Time delay

Microcontroller
XTAL1 1
XTAL2
TMachine cycle =
FXTAL

For F = 1GHz:
1
TMachine cycle = = 1 ns
1GHz

34
 Time delay
machine cycle
MOV R6, #19 1
MOV R0, #95 1
MOV R1, #5 1
ADD R6, R6, R0 1
ADD R6, R6, R1 1
5

Delay = 5 x T = 5 x 1 ns = 5 ns
machine cycle

35
 Time delay

machine cycle
MOV R6, #100
1
AGAIN: ADD R7,R7,R6 *100
1
*100
SUBS R6,R6,#1 1
BNE AGAIN 1/3 *100

Branch penalty

36
 Time delay

machine cycle
MOV R6, #50
1
AGAIN: NOP 1 *50
NOP 1 *50

SUBS R6,R6,#1 1 *50

BNE AGAIN 1/3 *50

37
 Time delay

machine cycle
MOV R7, #20
1
L1: MOV R6, #50
1 *20
L2: NOP
1 *20 * 50
NOP 1 *20 * 50
SUBS R6,R6,#1 1 *20 * 50
BNE L2 1/3 *20 * 50
SUBS R7,R7,#1 1 *20
BNE L1 1/3 *20

38
Stack

39
 Push and Pop

Push Pop

40
 Stack Pointer
 R13 is the stack pointer

 PUSH {Rn} 0x2000050

0x2000054
 SP = SP – 4 0x2000058
0x200005C
 [SP] = Rn 0x2000060
SP 0x2000064

 POP {Rn}
 Rn = [SP]
 SP = SP + 4

41
 Push and Pop (Cont.)
PUSH {register
list} POP {register list}
 PUSH {R10}  POP {R9}
 PUSH {R2,R3,R5}  POP {R4-R11}
 PUSH {R5-R9}  POP {R1-R4,R7}

42
 Stack

Addres Code
s
...
R0: 00000000
00000010 LDR R0,=0x10
LDR R1,=0x20
R1: 00000000
00000020 LDR R2,=0x30
R2: 00000030
00000000 0x00000010
PUSH {R0}
0x00000020
PUSH {R1}
0x00000030
PUSH {R2}
MOV R0,#0
MOV R1,#0
MOV R2,#0
POP {R2}

20005F0 POP {R1}

20005F4 POP {R0}
20005F8 L1 B L1
20005FC
2000600
SP Memor
y
43
 Stack Initialization
CPU Memory
20002000 00000000
00001001 00000004
SP (R13): 00000008

PC (R15): 00001000
Flash Boot
memory program

20000000
Stack
SRAM 20001FFF
20002000
3FFFFFFF

44
 Startup File
; memory allocation for stack Stack
Stack_Size EQU 0x00000400

AREA STACK, NOINIT, READWRITE, ALIGN=3

Stack_Mem SPACE Stack_Size
__initial_sp

; Heap Configuration Heap

Heap_Size EQU 0x00000200

AREA HEAP, NOINIT, READWRITE, ALIGN=3

__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit

PRESERVE8 Vector Table

THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size 45
Memory Allocation

Memory
__Vectors 20000600 00000000
080000ED 00000004
00000008

Flash
Reset_Handler Reset 080000ED
program
memory
SystemInit System init

__main main

Heap_Mem 20000000
Heap
200001FF
Stack_Mem 20000200
Stack SRAM
200005FF
__initial_sp 20000600

46
 Some stack usages
Nested calls
EXPORT __main
AREA MY_CODE, CODE, READONLY
__main
BL FUNC1
HERE B HERE

; subroutine FUNC1
FUNC1 PROC
PUSH {LR} ;store the LR on the stack
BL FUNC2 ;the func. call changes the LR
POP {LR} ;restore the LR value from the stack
BX LR
ENDP

; subroutine FUNC2
FUNC2 PROC
;do something
BX LR ; return
ENDP
END
47
 Some stack usages
Preserving registers values
EXPORT __main
AREA MY_CODE, CODE, READONLY
__main PROC
BL DELAY
HERE B HERE
ENDP

DELAY PROC
PUSH {R7} ;store R7 onto the stack
LDR R7,=120000
D_1 SUBS R7,R7,#1
BNE D_1
POP {R7} ;restore R7
BX LR
ENDP
END
48