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B7 Final Project

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15 views25 pages

B7 Final Project

Uploaded by

Pujitha Menda
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Design of Energy Efficient Adder for Low Power

Using CMOS Technology


by
G M MUKKARAM
AHMED(18AT1A0475)
BOYA NAVEEN(18AT1A0481)
R NITHESH REDDY (18AT1A0483)
MUTHYALA ROHITH (18ATIA04B1)
Under the Supervision of
S CHANDRA
LINGAMAIAH, M.Tech.
Assistant Professor
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
ENGINEERING
G PULLAIAH COLLEGE OF ENGINEERING AND
TECHNOLOGY
(An Autonomous Institute affiliated to JNTUA, Ananthapuramu)
2

CONTENTS

 ABSTRACT
 OBJECTIVES
 INTRODUCTION
 EXISTING METHOD
 PROPOSED METHOD
 SOFTWARE TOOL
 SIMULATED RESULTS
 CONCLUSION
 REFERENCES
ABSTRACT

• The importance of adder sub-systems are well known by every designers


and engineers. Hence the engineers are still doing research with them by
incorporating novel design techniques to speed up the circuit along with
power reduction.

• Adder logic-cells are used in many applications like within a


microprocessors, digital signal processors, etc., especially where the digital
data is being processed. A Complementary Metal Oxide Semiconductor
(CMOS) design techniques are implemented here with different logic styles.

• We implement some novel design ideas which will have less number of
transistors along with variable length and width of the transistors to
implement the addition.

3
OBJECTIVE

• A main objective of this work is to design low-power adder


circuits with the help of efficient XOR/NOR gates XOR gates are
being designed using transistors. Transistors are used in
designing full adders respectively

• This study focus more on reducing the layout area of the adder
design which in turn minimize the power Area, Power and
Speed are the three major optimization goals in the filed of VISI
domain.

4
EXISTING PROBLEM
• Since there are millions and millions of transistors are being integrated to
perform the function of the device, there is a huge amount of power is
being dissipated. This cause a major problem with reliability, since the chip
becomes heater.

• During the sleep or idle state of the device the transistors may leak some
current like reverso-biased PN junction leakage current, sub-threshold
current, etc. This is being referred to as static or leakage power dissipation
which is a major problem nowadays because of shrinking the technology.
Earlier this is not a major issue where the number of transistors are
minimum in a device.

• But with many more transistors, this will be a quite reasonable amount
compared to the dynamic power. By reducing the width or increasing the
length of a transistor, this leakage current can be minimized.

5
FULL ADDER SCHEMATIC DESIGN

• Any processor or a controller needs an ALU, performing all the basic


mathematical and comparative operations. Adders are the integral part of
the ALU and also very frequently invoked to generate address for various
branching instructions.

• An efficient adder design which dissipates low power may help to reduce the
overall power of the system.
FULL ADDER SCHEMATIC DESIGN
PROPOSED TECHNIQUE

• Any processor or a controller needs an ALU (Arithmetic Logic Unit),


performing all the basic mathematical and comparative operations.
Adders are the integral part of the ALU and also very frequently invoked
to generate addresses for various branching instructions. Adder sub-
systems play an immense role in the area of signal processing like during
the calculation of convolution. Fast Fourier Transform, etc. All kind of
multipliers like array multiplier and Wallace-Tree multiplier are being
designed with the help adder sub-systems.

• An efficient adder design which dissipates less power may help to reduce
the overall power of the system. The full adders with A. B. C in as inputs
and Sum, Cout as outputs can be implemented in several ways. It is
expressed as in Eq. 1, which is the most traditional method.
• Sum= A ⨁ B ⨁ Cin
• Cout = A.B+ Cin.(A ⨁ B)

8
TOOLS

It is a tool for designing and simulating circuits at layout level.


The tool features full editing facilities (copy, cut, past, duplicate,
move), various views (MOS characteristics, 2D cross section, 3D
process viewer), and an analog simulator.
 DSCH (DIGITAL SCHEMATIC)
 MICROWIND

9
DSCH2-SHORTCUT

10
MICROWIND2-SHORTCUT

11
SAMPLE OUTPUT

12
IMPLEMENTATION OF FULL ADDER
CONVENTIONAL STYLE

Fig: full adder conventional style design

13
IMPLEMENTATION OF FULL ADDER USING
6T-XOR DESIGN

Fig: FULL ADDER USING 6T-XOR DESIGN

14
IMPLEMENTATION OF FULL ADDER USING 4T-XOR
DESIGN

Fig: FULL ADDER USING 4T-XOR DESIGN


IMPLEMENTATION OF FULL ADDER USING 20T-
(WITHOUT XOR LOGIC) DESIGN

Fig: FULL ADDER USING 20T-(WITHOUT XOR)


LOGIC DESIGN
IMPLEMENTATION OF FULL ADDER USING 20T-(WITHOUT
XOR LOGIC) DESIGN

Fig: LAYOUT DESIGN OF FULL ADDER USING


20T-(WITHOUT XOR) LOGIC
IMPLEMENTATION OF FULL ADDER USING
20T-(WITHOUT XOR LOGIC) DESIGN

fig: Analog simulation of 20T full adder(without XOR)


IMPLEMENTATION OF FULL ADDER USING
3T-XOR DESIGN

Fig: FULL ADDER USING 3T USING XOR DESIGN


COMPARISION OF DIFFERENT DESIGNS
INTERMS OF VARIOUS PARAMETERS

Design Power(uW) Area(um2) Transistor count


Conventional 19.179 517.1 28
FA-6T XOR 9.038 365.9 24
FA-4T XOR 14.348 315.5 20
FA with 20T 9.172 270.9 20
FA-3T XOR 7.196 347.8 18

Fig: Comparison between designs in terms of


different parameters.(Need to be noted after
execution)
ADVANTAGES

• full swing output,


• low power consumption,
• high speed and robustness to supply voltage scaling,
• transistor sizing
CONCLUSION
• Adders are playing important roles for the operations like
multiplication, filtering, counting etc. They form foundations for most
of the bigger system designs. Here the XOR/XNOR gate design is
effectively being implemented by pass-transistor logic. An important
advantage of using this logic style is designing with less number of
transistors.

• This work can also be implemented in future with other kind of fast
adder sub-systems like carry look-ahead adder, carry-skip adder,
ripple carry adder, carry chain adders, etc. ECAD tools like Digital
Schematic (DSCH) and Microwind layout editor are used to
implement this study
FUTURE SCOPE
• Same study can be further extended to multiplier circuits
like array multipliers and Wallace-Tree multipliers.
Multipliers can be designed efficiently using carry-save
adders. Since, the multiplier can be designed using adders,
this study helps to design multipliers with low power.
REFERENCES
• D. Radhakrishnan, “Low-voltage low-power CMOS full adder,” IEE Proc.-Circuits Devices
Syst., vol. 148, no. 1, pp. 19–24, Feb. 2001.

• K. Navi, M. H. Moaiyeri, R. F. Mirzaee, O. Hashemipour, and B. M. Nezhad, “Two new low-


power full adders based on majority-not gates,

• I. Hassoune, D. Flandre, I. O’Connor, and J. Legat, “ULPFA: A new efficient design of a


power-aware full adder,” IEEE
• Elamaran, V., N.B.P. Reddy and K. Abhiram, 2012. Low power prescaler implementation in
CMOS VLSI. Proceedings of the International Conference on Emerging Trends in Electrical
Engineering and Energy Management, December 13-15, 2012, Chennai, India, pp: 16-19.

• Haghparast, M. and K. Navi, 2007. A novel reversible full adder circuit for nanotechnology
based systems. J. Applied Sci., 7: 3995-4000.

• Hu, J., X. Yu and J. Chen, 2011. New low-leakage flip-flops with power-gating scheme for
ultra-low power systems. Inform. Technol. J., 10: 2161-2167.

• Implementation of Low Power 1-bit Hybrid Full Adder using 22 nm CMOS Technology
Keerthana M Ravichandran T Electronics and Communication Engineering Electronics and
Communication Engineering SNS College of Technology (Anna University) SNS College of
Technology (Anna University) Coimbatore, Tamilnadu Coimbatore, Tamilnadu

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