COMBINATIONAL & SEQUENTIAL

CIRCUITS USING TTL 74XX ICs

UNIT VI
UNIT-VI

 COMBINATIONAL CIRCUITS USING TTL 74XX ICS: Study of

logic gates using 74XX ICs, 4-bit parallel adder (IC7483),
Comparator (IC 7485), Decoder (IC74138), Encoder
(IC74148), Multiplexer(IC 74151), Demultiplexer (IC 74154).

 SEQUENTIAL CIRCUITS USING TTL 74XX ICs: Flip Flops(IC

7474, IC 7473), Shift Registers (IC 74x164, IC 74x166),
Universal Shift Registers(IC 74194), 4-bit synchronous binary
counter(IC 74X163, 74X160).
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SEQUENTIAL CIRCUITS USING TTL
74XX ICs
What is Sequential logic?

 Sequential logic is defined as the digital logic whose output

is a function of present input and past output.

 So the sequential logic holds the binary data.

 Sequential logic elements are latches and flip-flops and

are used to design the sequential circuits.

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Block diagram

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Difference between combinational and
sequential circuits

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For 2 mark

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Basic elements of sequential circuit

 Flip Flop
 Latch

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Saturday, November 9, 2024 LINEAR AND DIGITAL IC APPLICATIONS - UNIT VI [WWW.TINYURL.COM/ECELDICA] 9
IC 7474

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Symbol & Truth Table

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With asynchronous inputs

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IC 7473 Master-slave J-K flip-flop

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Shift Registers
What is shift register?

 It is an n bit register with provision for shifting its stored

data by one bit position at each tick of clock .

 Applications
 Decoration purpose
 Communication

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Left Shift & Right shift

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Types of Shift register

 Serial in – Serial out shift register

 Serial in – Parallel out shift register
 Parallel in – Serial out shift register
 Parallel in – Parallel out shift register

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Serial in – Serial out shift register

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 The logic circuit provided above demonstrates a serial-in
serial-out (SISO) shift register.

 It comprises four D flip-flops that are interconnected in a

sequential manner.

 These flip-flops operate synchronously with one another, as

they all receive the same clock signal.

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 The synchronous nature of the flip-flops ensures that the
shifting of data occurs in a coordinated manner.

 When the clock signal rises, the input data is sampled and
stored in the first flip-flop.

 On subsequent clock pulses, the stored data propagates

through the flip-flops, moving from one flip-flop to the next.

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Serial in – Parallel out shift register

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Operation

 The basic operation of a SIPO shift register involves the

sequential transfer of data bits through a series of flip-flops.

 The register has one input line called the serial input (SI)
and parallel output lines (Q0, Q1, Q2, etc.) corresponding to
each flip-flop.

 The clock signal (CLK) controls the shifting of data.

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 Serial Input: Serial input (SI) is the entry point for the data into the shift register.
The data bits are fed into the first flip-flop in the register. On each clock pulse, the
data bit at the serial input is transferred to the first flip-flop and the existing data
in the register shifts by one position.

 Parallel Outputs: The parallel outputs (Q0, Q1, Q2, etc.) provide access to the
stored data in the shift register. Each flip-flop’s output is connected to a separate
output line, enabling simultaneous access to the stored data bits.

 Clock Signal: The clock signal (CLK) synchronizes the shifting of data within the
shift register. Typically, the clock edge triggers the transfer of data from one flip-
flop to the next. The rising or falling edge of the clock signal can be used,
depending on the specific implementation and requirements.
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Applications
1. Data Storage and Buffering: SIPO shift registers are used as temporary storage buffers
for data transfer between different devices operating at different speeds. They allow
serial data to be converted into parallel data, ensuring smooth communication between
different components of a system.

2. Serial-to-Parallel Conversion: In communication systems, SIPO shift registers are

employed to convert serial data streams received from external sources, such as sensors
or communication channels, into parallel forms for further processing or display purposes.

3. Address Decoding: SIPO shift registers are used for address decoding in memory
devices and microprocessors. They allow efficient selection of memory locations and
enable data retrieval or storage based on the specific address.

4. Control Systems: In control systems, shift registers are utilized to store and shift control
signals, enabling sequential operations and timing synchronization. They are often used
for generating timing sequences, control signals, and state machine implementations.

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Parallel in – Serial out shift register

A PISO shift register is a digital circuit that can accept

parallel data and output serial data.

 It is made up of a succession of flip-flops, with each flip-flop

capable of storing one bit of data.

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Saturday, November 9, 2024 LINEAR AND DIGITAL IC APPLICATIONS - UNIT VI [WWW.TINYURL.COM/ECELDICA] 26
Application of PISO Registers
• Serial Data Transmission: PISO shift registers are commonly used in applications where
parallel data needs to be transmitted over a serial communication channel. By converting
parallel data into a serial stream, PISO shift registers facilitate efficient data transmission
and enable compatibility with serial protocols.

• Sensor Data Acquisition: In sensor systems where data from multiple sensors is collected
simultaneously, a PISO shift register can be used to acquire and output the data in a
sequential manner. This allows for efficient processing and analysis of the sensor readings.

• Serial-to-Parallel Conversion: PISO shift registers can also be used to convert serial data
into parallel format. By loading the serial data into the shift register and then outputting it in
parallel, PISO shift registers enable interfacing between serial and parallel systems.

• Data Logging: PISO shift registers can serve as data logging elements where data from
different sources is sequentially stored and later accessed for analysis or further processing.

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Parallel in - Parallel out shift register

A PIPO shift register is its ability to load data and output it

in parallel.

 Unlike other shift registers that deal with serial input and
output, the parallel loading and output capabilities of a
PIPO shift register make it a powerful tool in many digital
systems.

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Saturday, November 9, 2024 LINEAR AND DIGITAL IC APPLICATIONS - UNIT VI [WWW.TINYURL.COM/ECELDICA] 29
Applications of PIPO Shift Registers
• Data storage: PIPO transfer registers are widely used for temporary data
storage in digital systems. The parallel upload feature provides fast data
entry, while the parallel output allows for on-demand data re-storage.

• Data Transfer: PIPO shift registers are used in applications where data
needs to be transferred from one location to another in a fast manner. By
loading the data in parallel and then outputting it simultaneously, PIPO
shift registers facilitate high-speed data transmission.

• Data Manipulation: PIPO shift registers are valuable for performing

various data manipulation operations, such as data sorting, arithmetic
calculations, and pattern recognition. The ability to process multiple bits of
data in parallel enhances the speed and efficiency of these operations.

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74LS164 [SIPO]

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Operation

 It is a SIPO shift register.

 Whenever CKR = 0 then all the outputs are zero.
 Short circuit pin 1 and 2 and apply inputs.
 Remaining operations is same as serial in parallel out shift
register.

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Shift Registers – 74166 [PISO]

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 SHIFT/LOAD =1  Shift the data from pin1

 SHIFT/LOAD =0  Load the data parallelly.

 Note: Both 74164 and 74166 are unidirectional shift

register.

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4- bit Universal Shift Register – 74X194

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Logic symbol

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Applications of Universal Shift Register

• Data Serializing/Deserializing: Data can be transferred

from parallel to serial format and vice-versa.
• Digital Signal Processing: Digital signal processing finds
its applications in arithmetic operations and data
manipulation.
• Delay Circuits: The circuits that introduce the delays in
digital signals are known as delay circuits.
• Frequency divider: obtains lower frequency clock
signals.
• Counters and timers: Counters and timers perform
timing and counting operations.
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Functional Table

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Ring Counter

 A ring counter is a typical application of the Shift register.

 The ring counter is almost the same as the shift counter.

 The only change is that the output of the last flip-flop is

connected to the input of the first flip-flop in the case of the
ring counter but in the case of the shift register it is taken as
output.

 Except for this, all the other things are the same.
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Ring counter circuit

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Truth Table

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Design 4 bit ring counter with single circulating
logic 1 using 74194
 Set input ABCD = 0001

 Load the data [S0 S1 = 1 1]

 Set IC to left shift [S0 S1 = 0 1]

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Circuit diagram

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Wave forms

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Design 4 bit ring counter with single circulating
logic 0 using 74194
 Set input ABCD = 1110

 Load the data [S0 S1 = 1 1]

 Set IC to left shift [S0 S1 = 0 1]

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Circuit

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Why self-correcting?

 Due to some hardware failure or noise ring counter enter

into invalid output state then itself enter into valid state.

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Saturday, November 9, 2024 LINEAR AND DIGITAL IC APPLICATIONS - UNIT VI [WWW.TINYURL.COM/ECELDICA] 49
Design a self correcting 4 bit 4 state Ring
counter with single circulating 1
A self correcting circuit is a circuit itself enter into invalid
output state to valid output state within a few clock cycle.

 Valid output states: 0001, 0010, 0100, 1000

 Invalid output states : 0000, 0011, 0101,0110, 0111,

1001, 1010, 1011, 1100, 1101, 1110, 1111 [12 states]

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Design

 Enable CLR [CLR=0] now QaQbQcQd = 0000

 Disable CLR [CLR = Vcc]
 Set left shift mode [S1S0 = 10]
 No need to connect any input, because it is self correcting
output
 Apply the clock then
 It will perform ring counting.

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Process

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Note

 Minimum number of clock cycles to correct itself 

 Maximum number of clock cycles to correct itself 

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Design a self correcting 4 bit 4 state Ring
counter with single circulating 0
A self correcting circuit is a circuit itself enter into invalid
output state to valid output state within a few clock cycle.

 Valid output states: 1110, 1101, 1011, 0111

 Invalid output states : 0000, 0001, 0010, 0011, 0100,

0101,0110, 1000, 1001, 1010, 1100, 1111 [12 states]

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Design

 Enable CLR [CLR=0] now QaQbQcQd = 0000

 Disable CLR [CLR = Vcc]
 Set left shift mode [S1S0 = 10]
 No need to connect any input, because it is self correcting
output
 Apply the clock then
 It will perform ring counting.

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Process

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JOHNSON COUNTER

 It is a n-bit shift register with the COMPLEMENT of the

serial output fed back into the serial input.

 It has 2n states.

 It is also called as Twisted ring counter / Moebius / Johnson

counter.

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Ring  Johnson counter

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Applications of Johnson counter
 Johnson counter is used as a synchronous decade counter or
divider circuit.

 It is used in hardware logic design to create complicated Finite states

machine. ex: ASIC and FPGA design.

 The 3 stage Johnson counter is used as a 3 phase square wave

generator which produces 1200 phase shift.

 It is used to divide the frequency of the clock signal by varying their

feedback.
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Design Johnson counter using 74x194

 No input required.
 Reset output by CLR=0
 Disable CLR
 Connect NOT gate between
Qa and Lin
 Start clock

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Truth Table

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Timing diagram

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Design self correcting 4 bit Johnson counter
using 7x194.
 In 4 bit Johnson counter 8 valid Invalid states are
stats are there. 1. 0010
Valid states are 2. 0100
1. 0001 3. 0101
4. 0110
2. 0011
5. 1001
3. 0111
6. 1010
4. 1111
7. 1011
5. 1110
8. 1101
6. 1100  Accidently counter enters into
7. 1000 above states how do you make
8. 0000 counter to enter valid state?
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Design
 Enable CLR for one clock then
disable it.
 Now output QaQbQcQd = 0000.
 Invert Qa and connect with Lin.
 Connect default input as 0001.
 No need to load input by
S1S0=11.
 Connect S1 with logic 1
 Control the S0 based on invalid
state.
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Saturday, November 9, 2024 LINEAR AND DIGITAL IC APPLICATIONS - UNIT VI [WWW.TINYURL.COM/ECELDICA] 66
 4-bit synchronous binary counter
(IC 74X163, 74X160).

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What is counter?
 Binary counter is a digital circuit that counts numbers in binary in the
form of series of flip lops.

 It is used to count the events or clock pulses.

 The state diagram of counter has single cycle.

 Modulus of a counter is the number of states in the counter.

 Counter with m states is called Modulo – m counter, also called as

divide by – m counter.
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Saturday, November 9, 2024 LINEAR AND DIGITAL IC APPLICATIONS - UNIT VI [WWW.TINYURL.COM/ECELDICA] 69
Types

 Ripple Counter

 Synchronous Counter.

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Ripple counter.
 These are the counters in
which we do not use universal
clock, main clock is only
applied to the first flip flop
and then for rest of flip flops
the output of previous flip flop
is taken as a clock.

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Saturday, November 9, 2024 LINEAR AND DIGITAL IC APPLICATIONS - UNIT VI [WWW.TINYURL.COM/ECELDICA] 72
Synchronous Counter

 These are the counters in which we use a universal clock

that is common to all flip flops. The Circuit diagram of
Synchronous Counter is given Below:

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74X163

 IC 74x163 is a integrated pre-settable synchronous 4 bit

modulo – 16 counter.
 It has 4 FF and operated by same clock pulse.

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PIN diagram

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Priority

1) CLR  CLR = 0 then QdQcQbQa = 0000

2) LOAD  LOAD = 0 then QdQcQbQa = DCBA
3) Enable signals.

RCO  Ripple Carry Output.

It generate logic 1 when counter output reach 1111.

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Saturday, November 9, 2024 LINEAR AND DIGITAL IC APPLICATIONS - UNIT VI [WWW.TINYURL.COM/ECELDICA] 79
Design 4 bit synchronous counter using 74X163

 Free running counter.

 No need to connect inputs

 Connect CLR=LOAD=ENT=ENP =1
 And apply clock

 Now it will count from 0 to 15.

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Design modulo - 11 counter for sequence 5 to
15
 Enable CLR by CLR = 0 and disable it. Now output is 0000.

 In the sequence starting value is 5  0101.

 Connect inputs to 5. [DCBA = 0001]

 After 1111 counter repeat from 0101. It means when RCO =1 then load
input data. [LOAD=0]

 Use NOT gate and connect RCO and LOAD

 Apply clock to start counting.

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Design

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Design modulo 11 counter for 0  10

 Counter starts from 0 so no input required. No need to

connect input pins. Enable CLR for 1 clock and disable it.

 Disable LOAD [LOAD = 1]

 Check the output and find 10  1010 then clear the output
by CLR = 0

Think how do you do above point in the circuit?

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Design

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Design a Decimal to Excess-3 counter

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 Counter starts from 3 so connect default input as DCBA =
0011

 Check the output and find 12  1100 then load the input by
LOAD = 0

Think how do you do above point in the circuit?

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Design

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74160 BCD Counter

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BCD counter

 It is a 16 pin BCD counter with a feature of count loading

means it is presettable.

 That means if you want you can count from anywhere

between 0 to 9. It is a positive edge triggered IC.

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 By using the A, B, C, and D data input pins we can set the
output pins QA, QB, QC, and QD to high or low.

 The active-low clear input resets the IC to 0000. The load

enables input (P) enables the count. load input loads data
inputs to counter on the positive edge of the clock.

 Pin 15 is the ripple carry output of this IC, it makes it very

easy to cascade multiple ICs to get a higher count.
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Circuit

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