COMBINATIONAL CIRCUIT

COMBINATIONAL CIRCUITS
 The combinational circuit has ‘n’ input
variables and ‘m’ output variables. Since, the
number of input variables is n, there are 2n
possible combinations of bits at the input.
Each output can be expressed in terms of
input variables by a Boolean expression.
ADDERS
 The most basic arithmetic operation is the
addition of two binary digits. A combinational
circuit that performs the addition of two 1-bit
numbers is called as half adder, and the logic
circuit that adds three 1-bit numbers is called
as full adder.
 2.1. Half Adder:

 The logic circuit that performs the addition of

two 1-bit numbers is called as half adder. It is

the basic building block for addition of two
single bit numbers. This circuit has two
outputs namely carry (C) and sum (S).
K–MAP SIMPLIFICATION FOR CARRY AND SUM:
 LOGIC DIAGRAM

Figure : Logic Diagram of Half Adder

 FULL ADDER
 A full adder circuit is an arithmetic circuit
block that can be used to add three bits to
produce a sum and a carry output. Let us
consider A and B as two 1-bit inputs & Cin is
a carry generated from the previous order bit
additions. Let S (sum) and Cout (carry) are
the outputs of the full adder.

Figure : Block Diagram of a Full Adder

TRUTH TABLE OF FULL ADDER
Inputs Outputs
A B Cin Sum (S) Carry Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 1 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1
K – MAP SIMPLIFICATION FOR
CARRY AND SUM:
 WE CAN REALIZE LOGIC DIAGRAM OF A
FULL ADDER USING GATES AS SHOWN IN
BELOW FIGURE:
LOGIC DIAGRAM OF FULL ADDER
USING TWO HALF ADDER AND OR
GATE
SUBTRACTOR
 A half subtractor is a combinational logic
circuit, which performs the subtraction of two
1-bit numbers. It subtracts one binary digit
from another to produce a DIFFERENCE
output and a BORROW output.
THE TRUTH TABLE OF HALF – SUBTRACTOR,
WHERE A, B ARE THE INPUTS, AND DIFFERENCE
(D) AND BORROW (B) ARE THE OUTPUTS

Inputs Outputs
A B D Bout
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Table : Truth table of Half –

Subtractor
K – MAP SIMPLIFICATION FOR DIFFERENCE AND
BORROW:

Figure : Logic Diagram of a Half subtractor

FULL SUBTRACTOR:
A full subtractor performs subtraction operation on
two bits, a minuend and a subtrahend

Figure : Block Diagram of a Full

subtractor
TRUTH TABLE OF FULL SUBTRACTOR:
Inputs Outputs

A B Bin D Bout

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1
K – map simplification for Difference
and Borrow:

Figure : Logic Diagram of a Full

Subtractor
 RIPPLE CARRY ADDER
An n-bit parallel adder can be constructed using n number of full
adders are connected in parallel and hence; it is also known as
parallel adder such that the previous carry or carry input for adder
0 is set to zero. The carry output of each adder is connected to the
carry input of the next higher order adder. Hence, it is also known
as carry propagate adder.

Figure : n-bit Binary Adder

Propagation Delay in Parallel Adder:
Parallel adders suffer from propagation delay problem because
higher bit additions depend on the carry generated from lower bit
addition. In effect, carry bits must propagate or ripple through all
stages before the most significant sum bit is valid. Thus, the total
sum (the parallel output) is not valid until after the cumulative
delay of all the adder.
CARRY LOOK AHEAD ADDER
The look ahead carry adder speeds up the operation by
eliminating this ripple carry delay. It examines all the input bits
simultaneously and also generates the carry in bits for all the
stages simultaneously. The method of speeding up the addition
process is based on the two additional functions of the full adder
called the carry generate and carry propagate functions.

Carry Generation:
Carry is generated only if both the input bits are 1, that is, if both
the bits A and B are 1’s, a carry has to be generated in this stage
regardless of whether the input carry Cin is a 0 or a 1. Let G as
the carry generation function,
G=A.B
Consider the present bit as the nth, then
Gn = An.Bn
Carry Propagation:
A carry is propagated if any one of the two input bits A or B is 1. If
both A and B are 0, a carry will never be propagated. On the
other hand, if both A and B are 1, then will not propagate the
carry but will generate the carry. Let P as the carry – propagation
function, then
Pn = An ⊕ Bn
Look ahead Expressions:
Let nth bit adder, the sum (S) and the carry out (C) for the nth
bit may be expressed in terms of the carry generation function
(G) and the carry propagation function (P) as
 DECODER
A decoder is a combinational circuit that
converts n input lines to a maximum of
unique output lines.
If n bit decoded information is not used or if
there are don’t care combination, the
decoder output will have less than
outputs.
3-TO-8 LINE DECODER
 The three input are decoded into eight output
, each output representing one of the
minterms of the 3 input variables. The three
inverter provide the complements of the
inputs, and each of the eight AND gates
generates one of the minterms .
 A particular application of decoder will be

binary to octal conversion..the input

variables may represent binary numbers and
the output will then represent the eight digits
in the octal number system.
BCD TO DECIMAL DECODER
ENCODERS
An encoders is consider to be a circuit which has multiple
input and generates a particular address as the output. If
there is only one active input, it is easy to encode. If
more than one input is active at a same time we have to
establish some priorities and such a device is called
priority encoder.
An encoder has input lines and n output lines
Octal to Binary Encoder
The 8 to 3 Encoder or octal to Binary encoder consists of 8
inputs: Y7 to Y0 and 3 outputs: A2, A1 & A0. Each input
line corresponds to each octal digit and three outputs
generate corresponding binary code

A2 = Y7 + Y6 + Y5 + Y4
A1 = Y7 + Y6 + Y3 + Y2
A0 = Y7 + Y5 + Y3 + Y1
PRIORITY ENCODER
It is a combinational logic circuit that comprises 2n input
lines and n output lines and depicts the high priority input
between all the input lines. When multiple input lines are
simultaneously active, the highest priority input is
considered first to produce output.

4 to 2 Priority Encoder
This is also called a 4-bit priority, which contains 4 inputs and 2
output lines as the encoder contains 2n number of input lines and
n number output lines. And, The third output is 'V', which is
considered a valid indicator but is set to 1 if more than one input
line is high or active (1).
If the valid bit is '0', every input is '0'. Here, the other two output
lines are depicted as don't care conditions symbolized by 'X'.
A 4 to 2 priority encoder has 4 inputs: Y3, Y2, Y1 & Y0, and 2
outputs: A1 & A0. Here, the input, Y3 has the highest priority,
whereas the input, Y0 has the lowest priority. In this case, even
if more than one input is ‘1’ at the same time, the output will be
the (binary) code corresponding to the input, which is
having higher priority. The truth table for the priority encoder is
as follows.
expression for A1
Expression for A0
 MULTIPLEXER
A multiplexer, abbreviated as MUX, is a digital switch which
selects one of the many inputs to a single output. A number of
control lines determine which input data is to be routed to the
output. If there are n select lines, then the number of maximum
possible input lines is and the multiplexer is referred to as a
–to-1 multiplexer or × 1 multiplexer.
2 x 1 MUX:
A 2 to 1 multiplexer has 2 inputs. Since 2 = 21, this multiplexer
will have one control (select) line. It has two data inputs I0 and
I1, one select input S, and one output.

Select Line
(S) Output Y
0 I0
1 I1
4 x 1 MUX:
A 4-to-1 multiplexer has 4 inputs and two select lines, where I0 to I3 are
the four inputs to the multiplexer, and S0 and S1 are the select lines.

Select Inputs
S1 S0 Output Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
APPLICATIONS OF MULTIPLEXERS
1. It is used as a data selector to select one out of many data
inputs.
2. They are used in designing the combinational circuits.
3. They are used in digital-to-analog and analog-to-digital
converters.
4. They can be used for simplification of logic design.
5. Multiplexers are also used in data acquisition systems.
DEMULTIPLEXER
The demultiplexer is a combinational logic circuit that performs the
reverse operation of a multiplexer. The demultiplexer has one input
line and m output lines. Again m = , so it requires n select lines. A
demultiplexer with one input and m output is called a 1-to-m
demultiplexer.
1 x 2 Demultiplexer:
A 1 to 2 demultiplexer has one input and two outputs. Since 2 = 2
to the power 1, it requires only one control (select) line.

Input
Select input Output
S S0 Y1 Y0
D 0 0 D

D 1 D 0
1 x 8 Demultiplexer:
A 1-to-8 demultiplexer has one input and eight outputs. Since 8 =
, it requires three select inputs
APPLICATIONS OF DEMULTIPLEXERS
Demultiplexers are used in
1. Data transmission
2. Implementation of Boolean Functions
3. Combinational logic circuit design
4. Generate enable signals (enable one out of many). The
application of enable signals in microprocessor systems
are:
a) Selecting different banks of memory
b) Selecting different input/output devices for data transfer
c) Enabling different functional units
d) Enabling different rows of memory chips depending on
address
COMPARATOR
The comparator is a combinational logic
circuit. It compares the magnitude of two
n-bit numbers and provides the relative
result as the output. Let A and B are the
two n-bit inputs. The comparator has three
outputs namely A > B, A = B and A < B.
Depending upon the result of comparison,
one of these outputs will go high.

1-bit Magnitude Comparator:

The 1-bit comparator is a
combinational logic circuit with
two inputs A and B and three
outputs namely A < B, A= B
and A < B.