CMOS Process Enhancements

(Transistors)
• Multiple threshold voltages and oxide thickness
• SOI(separate ppt given)
• High k-dielectric & low k-dielectric
• HEMT
• Plastic transistors
 CMOS Process Enhancements
• In the Analog, Digital or RF CMOS integrated
circuits along with transistors other elements
such as interconnects, resistors, capacitors are
to be integrated on chip.
• In order to achieve this, enhancements in
CMOS process technology is required.
 CMOS Process Enhancements
The main goals of adding CMOS enhancements
are :
 To provide on chip capacitors for analog
circuits.
 To provide on chip resistors.
 To provide routing of interconnects.
 CMOS Process Enhancements
The enhancements in CMOS technology are :

• Multilevel metal layers.

• Multilevel poly layers.
 Transistors
• To enhance the CMOS technology the bipolar
transistors can be integrated on chip in CMOS
technology and this forms the Bi-CMOS
technology. Here we will discuss the processing
requirements to make these devices on chip.
• Figure below shows the cross-section of Bi-CMOS
process in which NMOS and npn transistor are
fabricated on the same substrate.
NMOS – npn transistor
 NMOS – npn transistor
• The starting material is p substrate on which n type
epitaxial layer is grown.
• To form the NMOS transistor a p well is diffused in
selected area.
• And n+ diffusions form the source and drain
contacts.
• The n-epi layer is diffused with the p + diffusion
which forms the base for the npn transistor both
the devices i.e. NMOS and npn transistors are
isolated by field oxide.
Multiple threshold voltages
Multiple threshold voltages
Multiple threshold voltages
Multiple threshold voltages
Multiple threshold voltages
Oxide thickness
Oxide thickness
Oxide thickness
Oxide thickness
High k-dielectric & low k-dielectric
• The dielectric constant k, is a parameter
defining ability of material to store charge.
• In Si technology the reference value of k of
silicon di-oxide, SiO2, which is 3.9.
• Dielectrics featuring k > 3.9 are referred to as
“high”-k dielectric while dielectric featuring
k<3.9 are defined as “low”-k dielectrics.
• In cutting edge silicon nano-electronics both
high- and low-k dielectrics are needed to
implement fully functional very high-density
integrated circuit, although, for drastically
different reasons.
 Need for high-k dielectric
Silicon di-oxide (SiO2) has been used as a gate oxide
material for decades.
As transistors have decreased in size, the thickness of
the silicon dioxide gate dielectric has steadily
decreased to increase the gate capacitance and
thereby drive current, raising device performance.
As the thickness scales below 2 nm, leakage currents
due to tunneling increase drastically, leading to high
power consumption and reduced device reliability.
Replacing the silicon dioxide gate dielectric with a
high-k material allows increased gate capacitance
without the associated leakage effects.
 Need for low-k dielectric
In digital circuits, insulating dielectrics separate the
conducting parts (wire interconnects and
transistors) from one another.
As components have scaled and transistors are
closer together, the insulating dielectrics have
thinned to the point where charge build-up and
crosstalk adversely affect the performance of the
device.
Replacing the silicon di-oxide with a low-k
dielectric of the same thickness reduces parasitic
capacitance, enabling faster switching speeds and
lower heat dissipation.
High Electron Mobility Transistors
(HEMT)
 HEMT
• The HEMT or High Electron Mobility Transistor
is a type of field effect transistor (FET), that is
used to offer a combination of low noise figure
and very high levels of performance at
microwave frequencies.
• And the device is also used in RF design, where
high performance is required at very high RF
frequencies
 HEMT
• HEMT primarily works in depletion mode, i.e.
current flows through the device even with no
gate drive voltage. Voltage which has to be
applied on the gate electrode in order to stop
the current flow is called the pitch off voltage
Vp. The best way to understand the HEMT
electrical behavior is to develop a theorethical
model and simulate the I-V characteristics.
HEMT
HEMT
HEMT
HEMT
HEMT
Plastic Transistors
 Plastic Transistors
It is reported in “Radio e Televisione”, No.
9, March that the Russian scientist Nikolai
Semenof has set up a new type of transistor in
plastic material, which has properties similar to
those of normal germanium transistors.
 Plastic Transistors
• The plastic substance, bombarded by
radiation, becomes semiconducting. The
advantages of this new transistor are mainly
economic.
• Germanium is obtainable in comparatively
small quantities, while plastic materials can be
easily produced by (chemical) synthesis.
 Plastic Transistors
• The simple manufacture of inexpensive, high-
performance, wireless-capable, flexible Metal
Oxide Semiconductor Field Effect Transistors
(MOSFET) that overcome many of the operation
problems encountered in devices manufactured
using standard techniques.
• Created on large rolls of pliable plastic, these
MOSFETs could be used to make a host of devices
ranging from wearable electronics to bendable
sensors.
 Plastic Transistors
• Flexible semiconductors may not be a new concept by
flexible membranes with the products of recent research,
but the researchers say that this alternative, low-cost
process to produce such high-performance
semiconductors is particularly groundbreaking.
• Especially as they believe it could be easily scaled-up for
use in roll-to-roll processing of plastic sheets that would
enable semiconductor manufacturers to endlessly
replicate the etching patterns and mass-produce many
hundreds of thousands of devices on a single roll of
flexible plastic.
Plastic Transistors
INTERCONNECTS
 Interconnects
o The most important enhancement in CMOS
processes is the additions of signal and power
supply routing layers.
o The advantage of this type of routing is it
improves power and clock distribution to the
different modules inside the chip.
 Interconnects
The interconnect layers involved in process are :

(1) Metal interconnect

(2) Poly-silicon interconnect
(3) Local interconnect.
 Metal Interconnect
 The second layer of metal interconnect (Metal
2) is required for digital Integrated circuits.
 The connection between first metal layer
(Metal 1) and second metal layer (Metal 2) is
established with the help of via.
 For high speed chips third metal layer (Metal
3) is also required.
 Poly-silicon Interconnect
 Poly-silicon Interconnect layers are used in ICs
because of its high melting points as compare
to Aluminium (Al).
 But the major problem with poly-silicon
interconnect is it has high sheet resistance
because of this for long distance interconnects
this provides significant delay.
 Local Interconnect
 If silicide is used as a interconnect layer for
connecting different cells then it is called as
local interconnect.
 The important advantage of local interconnect
is it allows direct connection
between poly-silicon and diffusion regions.
 Due to this metal contacts are eliminated
which reduces the chip area.
CIRCUIT ELEMENTS
• Resistor
• Capacitor
Resistor
 Resistor
• In order to create the on chip resistors n-well or
poly-silicon materials can be used.
• The resistance of a material is a function of the
materials resistivity (Ã €) and the dimensions of the
material(Ã) ~ r à €
• Figure shows the slab of the material. The
resistance between the two leads A and B is given
as, R = × = Rsheet
where Rsheet is the sheet resistance of material
in W/square.
Capacitor
 Capacitor
• Figure shows the layout of capacitors used in integrated
circuits.
• As shown in Figure the capacitor can be formed by adding
extra poly silicon layer.
• In Figure (b) allows contacts to poly to be placed directly on
top of the thin oxide which is the isolation between two poly
plates. The bottom plate of the capacitor is made using poly
1 while the top plate where area determines the capacitance
is made using poly 2. A circular disc is used for poly 2.
• In Figure (a) the contact to poly is lying over the field region.
In this, sharp corners are avoided in the layout.
 Beyond Conventional CMOS

• SOI
• Dual Gate FETs
• Carbon Nano-Tubes
• Graphene FETs
Introduction
SOI
 ADVANTAGES of SOI
• It reduces parasitic induced capacitance.
• Improves performance.
• Complete electrical isolation.
• Less susceptible to radiation induced failure.
SOI Transistor
Dual Gate FETs
Dual Gate FETs
Dual Gate FETs
CNT
CNT
Graphene FETs
Graphene layer
References
Thank You