Machine Instructions and

Programs
 Objectives
 Machine instructions and program execution,
including branching and subroutine call and return
operations.
 Addressing methods for accessing register and
memory operands.
 Assembly language for representing machine
instructions, data, and programs.
 Program-controlled Input/Output operations.
 Memory Locations,
Addresses, and Operations
 Memory Location, Addresses, and Operation
n bits
first word
 Memory consists of second word

many millions of
storage cells, each of •
•
which can store 1 bit •
 Data is usually i th word

accessed in n-bit
groups •
•
 n is called word •

length last word

. Memory words.
Memory Example
Memory Location, Addresses, and Operation
 32-bit word length example
32 bits

b 31 b 30 b1 b0

•
•
•
Sign bit: b 31= 0 for positive numbers
b 31= 1 for negative numbers

(a) A signed integer

8 bits 8 bits 8 bits 8 bits

ASCII ASCII ASCII ASCII

character character character character

(b) Four characters

 Memory Location, Addresses, and Operation

 To retrieve information from memory, either for

one word or one byte (8-bit), addresses for each
location are needed.
 A k-bit address memory has 2k memory locations,
namely 0 – 2k-1, called memory space.
 24-bit memory: 224 = 16,777,216 = 16M (1M=220)
 32-bit memory: 232 = 4G (1G=230)
 1K(kilo)=210
Memory Location, Addresses, and Operation
Address Data Address Data
0 0
Address Data 1 1
0 2 2
1 3 3
2 4 4
3 5 5
4 6 …
5 7 …
6 8 …
7 9 …
… 29
14 30
3 bit Address
15 31
23 = 8 4 bit Address 5 bit Address
Address locations 0 to 7
 Memory Location,
Addresses
Address Data
0
1
2
3
4
5
…
…
2k-2
2k-1

K bit Address
2k combinations
Address locations 0 to 2k-1
Memory Location, Addresses, and Operation
 It is impractical to assign distinct addresses to
individual bit locations in the memory.
 The most practical assignment is to have successive
addresses refer to successive byte locations in the
memory – byte-addressable memory.
 Byte locations have addresses 0, 1, 2, …
 If word length is 16 bits, they successive words are
located at addresses 0, 2, 4,…
 If word length is 32 bits, they successive words are
located at addresses 0, 4, 8,…
 Byte and word address
Address Data Address Data Address Data
0 0 0
1 2 4
2 4 8
3 6
4 Word length: 4 bytes

5 Word length: 2 bytes

6
7

Word length: 1 byte

 Byte and word address
Address Data
0 74
1 78 Character ASCII

2 43 J 74
3 45 N 78
C 43
4
E 45
5
6
7
 Byte and word address
Word Word
Address Data Address Data Character ASCII

0 78 74 0 74 78 J 74
Word length 2 45 43 2 43 45 N 78
2 bytes C 43
4 4
E 45

Address Data Address Data

0 74 (J) 0 78 (N)
Word length 1 78 (N) 1 74 (J)
2 bytes NJ
JN 2 43 (C) 2 45 (E) EE
CE 3 45 (E) 3 43 (C)
4 4
 Big-Endian and Little-Endian
Assignments
Two ways
byte
address
are
assigned
across
words
 Big-Endian and Little-Endian
Assignments
Big-Endian: lower byte addresses are used for the most significant bytes of the word
Little-Endian: opposite ordering. lower byte addresses are used for the less significant bytes of the word

Word
address
Byte address Byte address
0 0 1 2 3 0 3 2 1 0

4 4 5 6 7 4 7 6 5 4

•
•
•
•
•
•

k k k k k
2k- 4 2k- 4 2k- 3 2k- 2 2k- 1 2 - 4 2- 1 2 - 2 2 -3 2 -4

(a) Big-endian assignment (b) Little-endian assignment

Byte and word addressing.
 Memory Location, Addresses, and Operation
 Address ordering of bytes
 Word alignment

Words are said to be aligned in memory if they begin at
a byte addr. that is a multiple of the number of bytes in
a word.
• 16-bit word: word addresses: 0, 2, 4,….
• 32-bit word: word addresses: 0, 4, 8,….
• 64-bit word: word addresses: 0, 8,16,….
 Access numbers, characters, and character strings
Instruction and Instruction
Sequencing
 Memory Operation
 Load (or Read or Fetch)
 Copy the content. The memory content doesn’t change.
 Address – Load
 Registers can be used
 Store (or Write)
 Overwrite the content in memory
 Address and Data – Store
 Registers can be used
 “Must-Perform” Operations
 Data transfers between the memory and the
processor registers
 Arithmetic and logic operations on data
 Program sequencing and control
 I/O transfers
 Register Transfer Notation (RTN)
 Identify a location by a symbolic name standing
for its hardware binary address (LOC, R0,DATAIN…)
 Contents of a location are denoted by placing
square brackets around the name of the location
 R1←[LOC]
 R3 ←[R1]+[R2]
 Assembly Language Notation
 Represent machine instructions and programs.

 MoveLOC, R1 ; = R1←[LOC] LOC 65

LOC + 1
- Copy the content of LOC to register R1

Initial value of R1=88

Content of LOC = 65

After Move operation: R1=65

Content of LOC = 65
 Assembly Language Notation
 Add R1, R2, R3 = R3 ←[R1]+[R2]
- Add the content of the registers R1 and R2 and
place the sum in register R3

Initial values R1=10, R2 =20, R3 = 90

After Add operation : R1=10, R2=20, R3=30

General format:
Operation operand(s)
 Three address instruction
Memory

A 40
 C=A+B B 30

C
C ← [A]+[B]
10

Instruction: Add A,B,C Memory

Format: A

Operation Source1, Source2, Destination B

If each operand takes k bits

- 2k bits + n bits to specify operation
 Two address instruction
Memory

Format:
A 40
B 30

Operation Source, Destination C 10

Instruction: Add A,B ; B ←[A]+[B]

 Destroys the content of Location B
 Alternate set of instructions
Memory
Move B,C A 40

Add A,C B
C
30
10

If each operand takes k bits

- 2k bits + n bits to specify operation
 Single address instruction
Format:
Operation operand(source/destination)
 Only one operand
Memory
 Another operand is implicit A 40
B 30
- A unique location – Accumulator C 10

Instruction:
Load A
Add B Example
Accumulator : 100
Store C
 CPU Organization
 Single Accumulator

Result usually goes to the Accumulator

Accumulator has to be saved to memory quite often
 General Register

Registers hold operands thus reduce memory traffic
 Stack

Operands and result are always in the stack
 Restrictions on operations
 Arithmetic operations allowed only in Registers
Instructions:
Move A, Ri
Move B, Rj
Add Ri, Rj
Store Rj,C
 Restrictions on operations
 Oneoperand can be in the memory another
operand in the register

Move A, Ri
Add B, Ri
Store Ri,C
 Instruction Formats
 Three-Address Instructions

ADD R1, R2, R3 ;R1 ← R2 + R3
 Two-Address Instructions

ADD R1, R2 ;R1 ← R1 + R2
 One-Address Instructions

ADD M ;AC ← AC + M[ADRS]
 Zero-Address Instructions

ADD ;TOS ← TOS + (TOS – 1)

Opcode Operand(s) or Addres(es)

 Instruction Formats
Example: Evaluate X=(A*B) + (C*D)
 Three-Address
1. Multiply A, B, R1 ; R1 ← [A] * [B]
2. Multiply C, D, R2 ; R2 ← [C] * [D]
3. Add R1, R2, X ; X ← [R1] + [R2]

A, B, C and D are memory address

 Instruction Formats
Example: Evaluate X=(A*B) + (C*D)
 Two-Address
1. Move A, R1 ; R1 ← [A]
2. Multiply B, R1 ; R1 ← R1 * [B]
3. Move C, R2 ; R2 ← [C]
4. Multiply D, R2 ; R2 ← R2 * [D]
5. Add R2, R1 ; R1 ← [R1] + [R2]
6. Move R1, X ; X ← [R1]

A, B, C and D are memory address

 Instruction Formats
Example: Evaluate X=(A*B) + (C*D)
 One-Address
1. Load A ; AC ← [A]
2. Multiply B ; AC ← [AC] * [B]
3. Store X ; X ← [AC]
4. Load C ; AC ← [C]
5. Multiply D ; AC ← [AC] * [D]
6. Add X ; AC ← [AC] + [X]
7. Store X ; X ← [AC]
A, B, C and D are memory address
 Instruction Formats
Example: Evaluate (A*B) + (C  D)
 Zero-Address
1. PUSH A ; TOS ← A
2. PUSH B ; TOS ← B
3. MUL ; TOS ← (A * B)
4. PUSH C ; TOS ← C
5. PUSH D ; TOS ← D
6. MUL ; TOS ← (C * D)
7. ADD ; TOS ← (C*D)+(A*B)
8. POP X ; M[X] ← TOS
A, B, C and D are memory address
 Using Registers
 Registers are faster
 Shorter instructions

The number of registers is smaller (e.g. 32 registers
need 5 bits)
 Potentialspeedup
 Minimize the frequency with which data is moved
back and forth between the memory and
processor registers.
 Instruction Execution and Straight-Line
Sequencing
Address Contents
Assumptions:
Begin execution here i Move A,R0 3-instruction  One memory operand per
i+4 Add B,R0 program instruction
i+8 Move R0,C segment  32-bit word length
 Memory is byte addressable
 Full memory address can be directly
A specified in a single-word
instruction

B Data for
the program
Two-phase procedure
 Instruction fetch
 Instruction execute
C

Figure : A program for C ¬ [A] + [B].

 i Move NUM1,R0

Branching i+4
i+8
Add NUM2,R0
Add NUM3,R0

•
•
i + 4n- 4 Add •
NUMn, Ro
i + 4n Move R0,SUM

•
•
SUM •
NUM1
NUM2

•
•
NUMn •

A straight-line program for adding n numbers.

counter=n;
sum=0;
repeat
sum= sum + NUM(i);
counter=counter-1;
until counter>0
printf(“%d”,sum);
 Additional instructions
 Clear Ri
Content of Register Ri is initialised to Zero
 Branch condition Label
Control transferred to specified location Label if
condition is satisfied
 Decrement Ri

Content of Register Ri is decremented by one

counter (Register R1 )=n; Move N, R1

sum(Register R0 )=0; Clear R0

repeat
sum= sum + NUM(i);
counter=counter-1; Decrement R 1

until counter>0
printf(“%d”,sum);
 Move N,R1
Clear R0

Branching LOOP
Determine address of
"Next" number and add
Program "Next" number to R0
loop
Decrement R1
Branch>0 LOOP
Branch target Move R0,SUM

Conditional branch

•
•
SUM
•
N n
NUM1
NUM2
•
•
•
NUMn
Figure: Using a loop to add n numbers.
 Condition Codes
 The processor keeps track of information about
the results of various operations for use by
subsequent conditional branch instructions

 Thisis accomplished by recording required

information in individual bits, often called
condition code flags
 Condition Codes
Four commonly used flags are
• N (negative)
• Z (zero)
• V (overflow)
• C (carry)
 Condition Codes
 Theseflags are usually grouped together in a
special processor register called the condition
code register or status register

 Individualcondition code flags are set to 1 or

cleared to 0, depending on the outcome of the
previous operation performed

 Different instructions affect different flags

 Condition Codes

N (negative): set to 1 if the results is negative; otherwise,
cleared to 0


Z (zero): set to 1 if the result is 0; otherwise, cleared to 0


V (overflow): set to 1 if arithmetic overflow occurs;
otherwise, cleared to 0


C (carry): set to 1 if a carry-out results from the operation
otherwise, cleared to 0


N and Z flags caused by an arithmetic or a logic operation,

V and C flags caused by an arithmetic operation
Status Bits
Condition Codes - Example
 Example: A: 11110000

A: 1 1 1 1 0 0 0 0+(−B): 1 1 1 0 1 1 0 0

B: 0 0 0 1 0 1 0 0 11011100

Z=0
C=1
S=1
V=0
A Program for C [A]+
[B]
Addressing Modes
 Generating Memory Addresses
 Can we give the memory operand address directly
in a single Add instruction in the loop?

 Use a register to hold the address of NUM1; then

increment by 4 on each pass through the loop

 How to specify the address of branch target?

 Addressing Modes
A high-level language enables the programmer to
use constants, local and global variables, pointers,
and arrays

 When translating a high-level language program into

assembly language, the compiler must be able to
implement these constructs using the facilities in the
instruction set of the computer

 Thedifferent ways in which the location of an

operand is specified in an instruction are
Addressing Modes
Opcode Operands
 Register mode

Operand is the contents of a processor register.

Address of the register (its Name) is given in the
instruction.
E.g. Clear R1 or Move R0, R1


 Programmer use register addressing to hold

variables that are frequently accessed
 Register Addressing
The instruction
indicates the data
register
Mo v e R0,R1

The source
operand is data
register R0
25 R0

R1
The Move R0, R1
instruction uses data
registers for both source
and destination operands
Register Addressing

Mo v e R0,R1

25 R0

R1

The destination operand is data

register R1
Register Addressing

Mo v e R0,R1

25 R0

25 R1

The effect of this instruction is to copy

the contents of data Register R0 in to
data register R1
 Absolute mode (Direct mode)

Operand is in a memory location.

Address of the memory location is given explicitly in the
instruction.

E.g. Clear A or Move LOC, R2


Also called as “Direct mode” in some assembly
languages


Register and absolute modes can be used to represent
variables
Absolute addressing

Memory
This instruction has a direct
Mo v e LOC ,R2
source operand

LOC 42
R2

The destination operand

The source operand
uses data register addressing
is in memory
Absolute addressing
The address of the operand
forms part of the instruction
Move LOC,R2

This is the actual operand

Loc 42
R2

Once the CPU has read the operand

address from the instruction, the
CPU accesses the actual operand
Absolute addressing

Memory

Mo v e LOC ,R2

LOC 42
42 R2

The effect of Move LOC,R2

is to read the contents of
memory location LOC and
copy them to R2
 Immediate mode

Operand is given explicitly in the instruction.

 E.g. Move 200immediate , R0


Uses # sign to indicate immediate operand


Move #200, R0


Can be used to represent constants.
 Immediate mode

Mo v e #4,R0

R0

The instruction Move #4, R0

uses a immediate source operand and
a register direct destination operand
Immediate mode

The immediate source operand,

4, is part of the instruction
Mo v e #4,R0

R0
Immediate mode

Mo v e #4,R0

R0

The destination operand is

a data register
 Immediate mode

Mo v e #4,R0

4 R0

The effect of this instruction is to

copy the immediate value 4
to register R0
 Example
 C=A+6
Move A, R1 : R1 ← [A]
Add #6, R1 : R1 ← [R1] + 6
Move R1, C Memory : C ← [R1]
A 44

C 50
50
44 R1
 Addressing modes (contd..)
 Register,Absolute and Immediate modes
contained either the address of the operand or the
operand itself.
 Some instructions provide information from which
the memory address of the operand can be
determined

That is, they provide the “Effective Address” of the
operand.

They do not provide the operand or the address of the
operand explicitly.
Effective address (EA)
 Indirection and Pointers
 Indirectmode: the effective address of the operand
is the contents of a register or memory location
whose address appears in the instruction

 Indirectionis denoted by placing the name of the

register or the memory address given in the
instruction in parentheses

 Theregister or memory location that contains the

address of an operand is called a pointer
 Addressing modes (contd..)
Effective Address of the operand is the contents of a register or a memory location whose
address appears in the instruction.

Add (R1),R0 Add (A),R0

Main
memory

B Operand A B

R1 B Register B Operand
•Register R1 contains Address B •Address A contains Address B
•Address B has the operand •Address B has the operand
R1 and A are called as “pointers”

This is called as “Indirect Mode”

 Addressing modes (contd..)
Effective Address of the operand is the contents of a register or a memory location whose
address appears in the instruction.

Add (R1),R0 Add R1,R0

Main
memory

B Operand R1 Operand

R1 B Register B
•Register R1 contains Address B
•Address B has the operand

This is called as “Indirect Mode”

 Addressing modes (contd..)
Effective Address of the operand is the contents of a register or a memory location whose
address appears in the instruction.

Add (A),R0 Add A,R0

Main
memory

A B A Operand

B Operand

•Address A contains Address B

•Address B has the operand

This is called as “Indirect Mode”

 Addressing Modes
 Indirect Address

Indicate the memory location that holds the address of the
memory location that holds the data

Move (A),R1

Mem. Location A = 101

100
101 0104
102
103
104 70
Using Indirect Addressing in a Program
Using Indirect Addressing in a
Program
Effective address (EA)
 Indexing and Arrays
 Index mode: the effective address of the operand is
generated by adding a constant value to the contents of a
register


The register used may be either a special register
provided for this purpose, or, more commonly, it may be
any one of a set of general purpose registers in the
processor.


It is referred to as an index register
 Indexing and Arrays

The index mode is useful in dealing with lists and arrays

Assembly syntax is X(Ri), where X denotes the constant
value contained in the instruction and Ri is the name of
the register involved.

The effective address of the operand is given by EA=X+
[Ri]

The contents of the index register are not changed in the
process of generating the effective address
 Addressing modes (contd..)
Effective Address of the operand is generated by adding a constant value to the contents of the
register

Add 20(R1),R0 •Operand is at address 1020

•Register R1 contains 1000
•Offset 20 is added to the
contents of R1 to generate the
1000 address 1020
•Contents of R1 do not change in the
offset = 20 process of generating the address
•R1 is called as an “index register”
1020 Operand
What address would be generated
by Add 1000(R1), R0 if R1 had 20?

R1 1000

This is the “Indexing Mode”

 Addressing Modes
 Indexed

EA = X + [Index Register]

Useful with X=2

“Autoincrement” or
“Autodecrement”
+

100
R1 = 100
101
Could be Positive or
Negative 102 110A
(2’s Complement) 103
104
Indexed Addressing
Indexed Addressing
An Example for Indexed Addressing

Student TEST TEST TEST3

ID 1 2
1
2
3
.
.
n
=SUM1 =SUM2 =SUM3
 An Example for Indexed Addressing

LIST+16+4
LIST+16+8
LIST+16+12
LIST+32
 Variations of Indexed
Addressing Mode

 A second register may be used to contain the offset X, in which case we

can write the Index mode as (Ri,Rj)

The effective address is the sum of the contents of registers Ri and Rj

The second register is usually called the base register

This mode implements a two-dimensional array

 Another version of the Index mode use two registers plus a constant,
which can be denoted as X(Ri,Rj)

The effective address is the sum of the constant X and the contents of
registers Ri and Rj

This mode implements a three-dimensional array
Effective address
 Addressing Modes
(contd..)
 Autoincrement mode:

Effective address of the operand is the contents of a
register specified in the instruction.

After accessing the operand, the contents of this
register are automatically incremented to point to the
next consecutive memory location.

Ex. Add (R2)+, R0
 Before execution: R2=1000, [1000]=30, R0=10
 After execution: R2=1004, [1000]=30, R0= 40
Using Indirect Addressing in a Program
Using Indirect Addressing in a
Program
An Example of Autoincrement
Addressing
 Addressing Modes
(contd..)
 Autodecrement mode

Effective address of the operand is the contents of a register specified
in the instruction.

Before accessing the operand, the contents of this register are
automatically decremented to point to the previous consecutive
memory location.

Ex. Add -(R2), R0
 Before execution: R2=1000, [0996]=30, R0=10
 After execution: R2=0996, [0996]=30, R0= 40

 Autoincrement and Autodecrement modes are useful for

implementing “Last-In-First-Out” data structures.
 Effective address (EA)
 Implicitly the increment
and decrement amounts
are 1.

This would allow us to access individual
bytes in a byte addressable memory.

 Recall that the information

is stored and retrieved one
word at a time.

In most computers, increment and
decrement amounts are equal to the
word size in bytes.

 E.g., if the word size is 4

bytes (32 bits):

Autoincrement increments the contents
by 4.

Autodecrement decrements the
contents by 4.
 Relative addressing
•Effective Address of the operand is generated by adding a constant value to the
contents of the Program Counter (PC).

•Variation of the Indexing Mode, where the index register is the PC instead of a
general purpose register.

•When the instruction is being executed, the PC holds the address of the next
instruction in the program.

•Useful for specifying target addresses in branch instructions.

•Addressed location is “relative” to the PC, this is called “Relative Mode”

92
 Addressing Modes
 Relative Address
0

EA = X + [PC] 1
PC = 2 2

100
X = 100
101
102 110A
Could be Positive or 103
Negative 104
(2’s Complement)
 Relative Addressing
 X(PC) – note that X is a signed number
 Branch>0 LOOP
 This location is computed by specifying it as an offset from the
current value of PC.
 Branch target may be either before or after the branch instruction,
the offset is given as a singed num.
 Branch>0 LOOP
-16(PC)
1000

1012
1016
 Effective address (EA)
 Implicitly the increment and
decrement amounts are 1.

This would allow us to access individual
bytes in a byte addressable memory.

 Recall that the information

is stored and retrieved one
word at a time.

In most computers, increment and
decrement amounts are equal to the word
size in bytes.

 E.g., if the word size is 4

bytes (32 bits):

Autoincrement increments the contents by
4.

Autodecrement decrements the contents
by 4.
Basic Input/Output
Operations
 Input /Output
 Thedata on which the instructions operate are not
necessarily already stored in memory.

 Dataneed to be transferred between processor

and outside world (disk, keyboard, etc.)

 I/O
operations are essential, the way they are
performed can have a significant effect on the
performance of the computer.
 Program-Controlled I/O
Example
 Read in character input from a keyboard and produce character
output on a display screen.

 Rate of data transfer (keyboard, display, processor)

 Difference in speed between processor and I/O device creates the
need for mechanisms to synchronize the transfer of data.
 A solution: on output, the processor sends the first character and
then waits for a signal from the display that the character has been
received. It then sends the second character.
 Input is sent from the keyboard in a similar way.
Program-Controlled I/O Example

Bus

Processor
DATAIN DATAOUT

- Registers SIN SOUT

- Flags
- Device interface Keyboard Display

Bus connection for processor, Keyboard and display

.
SIN = 1 Character is struck from keyboard
SOUT = 1 Display is ready to receive character
 Program-Controlled I/O Example

 Machine instructions that can check the state of

the status flags and transfer data:

READWAIT Branch to READWAIT if SIN = 0

Input from DATAIN to R1

WRITEWAIT Branch to WRITEWAIT if SOUT = 0

Output from R1 to DATAOUT
 Program-Controlled I/O Example
Memory-Mapped I/O
 Some memory address values are used to refer to peripheral device
buffer registers.
(DATAIN, DATAOUT)

 No special instructions are needed.

 Data can be transferred between these registers and the processor

using instructions such as Move, Load or Store.

 Also use device status registers.

(INSTATUS, OUTSTATUS)

- Bit B3 is used for SIN and SOUT

 Data and Status
Registers
DATAIN

DATAOUT

INSTATUS DIRQ KIRQ SOUT SIN

OUTSTATUS DIRQ KIRQ

 Program-Controlled I/O Example
READWAIT Testbit #3, INSTATUS
Branch=0 READWAIT
MoveByte DATAIN, R1

WRITEWAIT Testbit #3, 0UTSTATUS

Branch=0 WRITEWAIT
MoveByte R1, DATAOUT
Program that reads a line of characters and
display it
 Program that reads a line of
characters and display it
Move #LOC, R0 ; Initialize pointer register RO to point to the address of the first
location in memory where the characters are to be stored
READ TestBit #3, INSTATUS ; Wait for a character to be entered in the keyboard buffer DATAIN.
Branch=0 READ;
MoveByte DATAIN, (R0) ; Transfer the character from DATAIN into the memory
(this clears SIN to 0).
ECHO TestBit #3, OUTSTATUS ; Wait for the display to become ready
Branch=0 ECHO
MOVEByte (R0), DATAOUT ; Move the character just read to the display buffer register
(this dears SOUT to 0).
Compare #CR, (R0)+ ; Check if the character just read is CR (carriage return).
If it is not CR, then branch back and read another character
Branch != READ Also, increment the pointer to store the next character.
 Program-Controlled I/O Example
 Assumption – the initial state of SIN is 0 and the
initial state of SOUT is 1.

 Any drawback of this mechanism in terms of

efficiency?

Two wait loops  processor execution time is wasted

 Alternate solution?

Interrupt