Module 2

Sequential Logic: Introduction, Sequential Circuits,

Storage Elements: Latches, Flip-Flops
Objective
1. Explain in words the operation of S-R and gated D latches.
2. Explain in words the operation of D, D-CE, S-R, J-K, and T flip-flops.
3. Make a table and derive the characteristic (next-state) equation for
such latches and flip-flops. State any necessary restrictions on the
input signals.
4. Draw a timing diagram relating the input and output of such latches
and flip-flops.
5. Show how latches and flip-flops can be constructed using gates.
Analyze the operation of a flip-flop that is constructed of gates and
latches.
2
Introduction
• Sequential switching circuits have the property that the output
depends not only on the present input but also on the past sequence
of inputs.
• In effect, these circuits must be able to “remember” something about
the past history of the inputs in order to produce the present output.
• Latches and flip-flops are commonly used memory devices in
sequential circuits.
• A memory element that has no clock input is often called a latch.
• A memory element that has clock input is often called a Flip-Flop.

3
Introduction
• The switching circuits that we have studied so far have not had
feedback connections.
• By feedback we mean that the output of one of the gates is
connected back into the input of another gate in the circuit so as to
form a closed loop.
• Sequential circuits must contain feedback, but not all circuits with
feedback are sequential.
• There are a few circuits containing feedback that are combinational.

4
Introduction
• Consider the below circuit , an oscillator can be created using any
odd number of inverters.
• The oscillator waveform has a high and a low time that is the sum
of the propagation times of the inverters.
• For example, with n inverters and with all having the same delay, the
oscillator waveform high time is (n + 1)/2 times the high-to-low inverter
propagation delay plus (n − 1)/2 times the low-to-high inverter
propagation delay.

5
Introduction

• Consider a feedback loop,

• In this case, the circuit has two stable conditions, often referred to as
stable states.
• The simple loop of two inverters lacks (absence of) any external
means of initializing the state to one of the stable states.

6
Questions
• Assume that the inverter in the given circuit has a propagation delay
of 5 ns and the AND gate has a propagation delay of 10 ns. Draw a
timing diagram for the circuit showing X, Y, and Z. Assume that X is
initially 0, Y is initially 1, after 10 ns X becomes 1 for 80 ns, and then
X is 0 again.

7
Set-Reset Latch
• NOR-Gate latch
• The basic flip-flop can be improved by replacing the inverters with
either NAND or NOR gates.
• The additional inputs on these gates provide a convenient means for
application of input signals to switch the flip-flop from one stable
state to the other.

8
Set-Reset Latch
• Two inputs labelled R and S.
• Two outputs, defined in more general
terms as Q and Q’.

9
Set-Reset Latch
• To aid in understanding the operation of this circuit,
recall that an H = 1 at any input of a NOR gate
forces its output to an L = 0.
• The first input condition in the truth table is R = 0
and S = 0. Since a 0 at the input of a NOR gate has
no effect on its output, the flip-flop simply remains
in its present state; that is, Q remains unchanged.

10
Set-Reset Latch
• The second input condition R = 0 and S = 1 forces
the output of NOR gate B low.
• Both inputs to NOR gate A are now low, and the
NOR-gate output must be high.
• Thus a 1 at the S input is said to SET the flip-flop,
and it switches to the stable state where Q = 1.

11
 Set-Reset Latch
• The third input condition is R = 1 and S = 0. This
condition forces the output of NOR gate A low,
and since both inputs to NOR gate B are now low,
the output must be high.
• Thus a 1 at the R input is said to RESET the flip-flop
and it switches to the stable state where Q = 0 (or
Q’ = 1).

12
Set-Reset Latch
• The last input condition in the table, R = 1 and S = 1, is
forbidden, as it forces the outputs of both NOR gates
to the low state.
• In other words, both Q = 0 and Q’ = 0 at the same
time.
• This violates the basic definition of a flip-flop that
requires Q to be the complement of Q’, and so it is
generally agreed never to impose this input condition.

13
 Set-Reset Latch
• Timing Diagram for S-R Latch
• At t1, S = 0 → 1, Q = 0 → 1 a short time (ε) later.
• ε represents the response time or delay time of the
latch.
• At t2, S = 1 → 0, Q = No change (NC).
• At t3, R = 0 → 1, and Q = 1 → 0 a short time (ε) later.
• The duration of the S (or R) input pulse must
normally be at least as great as ε in order for a
change in the state of Q to occur.
• If S = 1 for a time less than ε, the gate output will not
change and the latch will not change state.`

14
Set-Reset Latch
• Meta-stable State:
• Two-inverter circuit and the set-reset circuit can exist a third stable
state called metastable state.
• This is the situation where the voltage level at the output of the two
inverters or gates is approximately halfway between the voltage
levels for a logic 0 and a logic 1.
• This state is referred to as a metastable state.
• It is metastable because any noise existing in the circuit will cause the
circuit to transition to one of the truly stable states.

15
 Set-Reset Latch
• Metastable State:
• However, certain events can cause the latch to enter the metastable state
for a short time.
• The simultaneous change in S and R from 1 to 0 in the set-reset latch can
cause the latch to enter the metastable state.
• Starting with Q = 0 and applying a pulse on S with a length on the
borderline between being too short to cause Q to change and just long
enough to cause Q to change may cause the circuit to enter the
metastable state.
• Events causing the circuit to enter the metastable state must be avoided

16
 Set-Reset Latch
• The term present state to denote the state of the Q output of the latch
or flip-flop at the time any input signal changes, and the term next
state to denote the state of the Q output after the latch or flip-flop has
reacted to the input change and stabilized.
• Let Q(t) represent the present state and Q(t +ε) or Qn or Q+ represent
the next state, an equation for Q(t+ε) can be obtained from the circuit
can write:

17
Set-Reset Latch
• Derivation of Q+ for an S-R Latch
• Next-state equation or characteristic equation is
• Q+ = S + R′Q

18
 Questions
• This problem illustrates the improper operation that can occur if both inputs to an S-R
latch are 1 and are then changed back to 0. For Figure shown below, complete the
following timing chart, assuming that each gate has a propagation delay of exactly 10
ns. Assume that initially P = 1 and Q = 0. Note that when t = 100 ns, S and R are both
changed to 0. Then, 10 ns later, both P and Q will change to 1. Because these 1’s are
fed back to the gate inputs, what will happen after another 10 ns?

19
Set-Reset Latch
• Complete the following timing diagram for an S-R latch. Assume Q
begins at 1.

20
Set-Reset Latch
• Switch Debouncing with an S-R Latch
• When a mechanical switch is opened or closed, the switch contacts
tend to vibrate or bounce open and closed several times before
settling down to their final position.
• This produces a noisy transition, and this noise can interfere with the
proper operation of a logic circuit.

21
Set-Reset Latch
• Switch Debouncing with an S-R Latch
• The pull-down resistors connected to contacts a and b assure that
when the switch is between a and b the latch inputs S and R will
always be at a logic 0, and the latch output will not change state.

22
 Set-Reset Latch
• Switch De-bouncing with an S-R Latch
• The timing diagram shows what happens when the
switch is flipped from a to b.
• As the switch leaves a, bounces occur at the R
input; when the switch reaches b, bounces occur
at the S input.
• After the switch reaches b, the first time S
becomes 1, after a short delay the latch switches to
the Q = 1 state and remains there.
• Thus Q is free of all bounces even though the
switch contacts bounce.

23
Set-Reset Latch
• latch

24
Gated Latches
• Gated latches have an additional input called the gate or enable input.
• When the gate input is inactive, the state of the latch cannot change.
• When the gate input is active, the latch is controlled by the other
inputs and operates as indicated in the preceding section.

25
 Gated Latches
• Race Condition in the Gated S-R Latch
• Another reason for disallowing the S = R = 1 input combination is
illustrated by considering a change in G from 1 to 0 with S = R = 1.
• When G changes, both inputs to the basic S-R latch change from 0 to 1.
This causes both gates in the basic S-R latch to attempt to change from
1 to 0; a race condition exists and the propagation delays of the gates
determine whether the latch stabilizes with Q = 0 or Q = 1.

26
 Gated Latches
• Q+ has a static 1-hazard for the input combinations
• G = 1, S = 1, R = 1, Q = 1 and G = 0, S = 1, R = 1, Q = 1.
• when G changes from 1 to 0 (or 0 to 1) between these two
input combinations, it is possible for Q to change from 1 to 0
so, the hazard may cause a glitch in Q,

27
Gated Latches
• Catching Problem:
• This is restriction in gated S-R latches.
• The S and R inputs must not be changing or contain glitches while G = 1.
• For example, assume Q = 0 when G = 0 → 1 and S = 0 and R = 0.
• If S = R = 0 until G returns to 0, then Q remains at 0.
• If S contains a 1 glitch, due to a static 1-hazard then Q may be forced to a 1 and will
remain there after G becomes 0.
• A similar problem occurs if S does not change from 1 to 0 until after G changes to 1.
• This is referred to as the 1’s catching problem.
• So to avoid S=R=1 next is D-Latch

28
Gated Latches
• Gated D Latch (or Transparent latch)
• It can be obtained from a gated S-R latch by connecting S to D and R
to D′.

29
Gated Latches
• Unreliable Gated D Latch Circuit
• Most digital systems use a clock signal to synchronize the change in
outputs of the system’s flip-flops to an edge of the clock signal, either
the positive (0 to 1) or the negative (1 to 0) edge of the clock.
• Flip-flops where the clock signal is connected to the gate inputs of the
latches

30
Gated Latches
• In the circuit shown,
• when the Clk = 1 so Q = Q′ when the input x = 1
• and Q = Q when x = 0.
• When Clk = 1 and x = 1, D = Q′ causes Q to change and, if Clk remains
1, the change in Q will feed back and cause Q to change again. If Clk
remains at 1, Q will oscillate.
• Consequently, the circuit will only operate as intended if Clk remains
at 1 for a short time; it has to 1 just long enough to allow Q to change
but short enough to prevent the change from feeding back and
causing a second change.
31
 Gated Latches
• With a single latch, it may be possible to control the clock high time so the latch
operates as intended, but in a system with several latches, the variation in gate
delays would make it impossible to provide the correct clock width to all latches.
• To avoid this timing problem, more complicated flip-flops restrict the flip-flop
outputs to only change on an edge of the clock, and the outputs cannot
change at other times even if the inputs change.
• If the inputs to the flip-flop only need to be stable for a short period of time
around the clock edge, this refer to the flip-flop as edge-triggered.
• The term master-slave flip-flop refers to a particular implementation that uses
two gated latches in such a way that the flip-flop outputs only change on a clock
edge.
32
Difference between latch and flip flop

33
• Design a gated D latch using only NAND gates and one inverter.

34
Edge-Triggered D Flip-Flop
• If the output of flip-flop can change in response to a 0 to 1 transition
on the clock input, we say that the flip-flop is triggered on the rising
edge (or positive edge) of the clock. (rising-edge trigger)
• If the output can change in response to a 1 to 0 transition on the clock
input, we say that the flip-flop is triggered on the falling edge (or
negative edge) of the clock. (falling-edge trigger).
• The term active edge refers to the clock edge (rising or falling) that
triggers the flip-flop state change.

35
Edge-Triggered D Flip-Flop
• D Flip-Flops

• Timing for D Flip-Flop (Falling-Edge Trigger)

36
Edge-Triggered D Flip-Flop
• D Flip-Flop (Rising Edge Trigger)
• A rising-edge-triggered D flip-flop can be constructed from two gated
D latches and an inverter

37
Edge-Triggered D Flip-Flop
• D Flip-Flop (Rising Edge Trigger)

38
Edge-Triggered D Flip-Flop
• D Flip-Flop (Rising Edge Trigger)
• When CLK = 0, G1 = 1, and the first latch P = D input.
• Because G2 = 0, the second latch holds the current value of Q.
• When CLK = 0 → 1, G1 =1 → 0, and the current value of D is stored in
the first latch, at same time G2 = 1, the value of Q = P.
• When CLK changes back to 0, the second latch takes on the value of P
and holds it and, then, the first latch starts following the D input again.
• If the first latch starts following the D input before the second latch
takes on the value of P, the flip-flop will not function properly.

39
Edge-Triggered D Flip-Flop
• D Flip-Flop (Rising Edge Trigger)
• Therefore, the circuit designers must pay careful attention to timing
issues when designing edge-triggered flip-flops.
• With this circuit, output state changes occur only following the rising
edge of the clock.
• The value of D at the time of the rising edge of the clock determines
the value of Q, and any extra changes in D that occur between rising
clock edges have no effect on Q.

40
Edge-Triggered D Flip-Flop
• Because a flip-flop changes state only on the active edge of the clock, the
propagation delay of a flip-flop is the time between the active edge of the clock
and the resulting change in the output.
• There are also timing issues associated with the D input.
• To function properly:
• The D input to an edge-triggered flip-flop must be held at a constant value for a period of time before and
after the active edge of the clock.
• If D changes at the same time as the active edge, the behavior is unpredictable.

• The amount of time that D must be stable before the active edge is called the
setup time (tsu),
• The amount of time that D must hold the same value after the active edge is the
hold time (th). 41
Edge-Triggered D Flip-Flop
• Setup and Hold Times for an Edge-Triggered D Flip-Flop

• The times at which D is allowed to change during the clock cycle are shaded in the timing diagram.
• The propagation delay (tp) from the time the clock changes until the Q output changes is also
indicated.

42
 Edge-Triggered D Flip-Flop

• The setup time allows a change in D to propagate through the first latch
before the rising edge of Clock. The hold time is required so that D gets
stored in the first latch before D changes. 43
Edge-Triggered D Flip-Flop
• Determination of Minimum Clock Period

• Suppose the inverter has a propagation delay of 2 ns,

• The flip-flop has a propagation delay of 5 ns and a setup time of 3 ns.
44
 Edge-Triggered D Flip-Flop
Determination of Minimum Clock Period
• That the clock period is 9 ns, i.e., the time between successive active edges
(rising edges for this figure).
• Then, 5 ns after a clock edge, the flip-flop output will change, and 2 ns
after that, the output of the inverter will change.
• Therefore, the input to the flip-flop will change 7 ns after the rising edge,
which is 2 ns before the next rising edge.
• But the setup time of the flip-flop requires that the input be stable 3 ns
before the rising edge; therefore, the flip-flop may not take on the correct
value.
45
Edge-Triggered D Flip-Flop
Determination of Minimum Clock Period
• Now the clock period is 15 ns
• Again, the input to the flip-flop will change 7 ns after the rising edge.
• However, because the clock is slower, this is 8 ns before the next
rising edge.
• Therefore, the flip-flop will work properly.
• Note in Figure (c) that there is 5 ns of extra time between the time
the D input is correct and the time when it must be correct for the
setup time to be satisfied.

46
 Edge-Triggered D Flip-Flop
Determination of Minimum Clock Period
• We can use a shorter clock period, and have less extra time, or no extra
time.
• Figure (d) shows that 10 ns is the minimum clock period which will work
for this circuit.

47
 Questions
• What change must be made in following circuit to implement a falling-
edge-triggered D flip-flop? Complete the following timing diagram for
the modified flip-flop.

48
Questions
• Fill in the timing diagram for a falling-edge-triggered S-R flip-flop.
Assume Q begins at 0.

49
S-R Flip-Flop
• An S-R flip-flop is similar to an S-R latch in that S = 1 sets the Q output to 1, and R
= 1 resets the Q output to 0.
• The essential difference is that the flip-flop has a clock input, and the Q output
can change only after an active clock edge.

S R Q+
0 0 Q
0 1 0
1 0 1
1 1 Not
used

50
S-R Flip-Flop
• S-R Flip-Flop Implementation and Timing

51
S-R Flip-Flop
S-R Flip-Flop Implementation and Timing
• This flip-flop changes state after the rising edge of the clock.
• The circuit is often referred to as a master-slave flip-flop.
• When CLK = 0, the S and R inputs set the outputs of the master latch to the appropriate value
while the slave latch holds the previous value of Q.
• When CLK = 0 → 1, the value of P is held in the master latch and this value is transferred to
the slave latch.
• The master latch holds the value of P while CLK = 1, and, hence, Q does not change.
• When the clock changes from 1 to 0, the Q value is latched in the slave, and the master can
process new inputs.
• In timing diagram Initially, S = 1 and Q changes to 1 at t1. Then R = 1 and Q changes to 0 at t3.

52
S-R Flip-Flop
• S-R Flip-Flop Implementation and Timing

53
 S-R Flip-Flop
• S-R Flip-Flop Implementation and Timing
• For a rising-edge-triggered flip-flop the value of the inputs is sensed at the
rising edge of the clock, and the inputs can change while the clock is low.
For the master-slave flip-flop, if the inputs change while the clock is low,
the flip-flop output may be incorrect.
• For example, in timing diagram
• At t4, S = 1 and R = 0, so P = 1.
• At t5, S = 0 , but P does not change, Q = 1 after the rising edge of CLK.
• However, at t5, S = R = 0, so the state of Q should not change.
• We can solve this problem if we only allow the S and R inputs to change
while the clock is high.
54
J-K Flip-Flop
• Master-Slave J-K Flip-Flop (Q Changes on Rising Edge)
• Two S-R latches connected in a master-slave arrangement except S
and R have been replaced with J and K, and the Q and Q′ outputs are
feeding back into the input gates.
• Because S = J·Q′·CLK′ and R = K·Q·CLK′, only one of S and R inputs to
the first latch can be 1 at any given time.

55
J-K Flip-Flop

56
 J-K Flip-Flop
• Lab Experiment:
• Realize a J-K Master-Slave Flip-Flop using NAND gates and verify its
truth table.

Input Output
J J K Qn+1
Q 0 0 Qn
0 1 0
CLK
Q 1 0 1
1 1
K
Q+ = JQ′ + K′Q

57
 J-K Flip-Flop
• Lab Experiment: Write HDL code for a J-K Master-Slave Flip-Flop.
if rising_edge(Clock) then
entity JK_FF_VHDL is
if (J='0' and K='0') then
port( J,K: in std_logic;
Clock: in std_logic; temp <= temp;
Output: out std_logic); elsif (J='0' and K='1') then
end JK_FF_VHDL; temp <= '0';
elsif (J='1' and K='0') then
architecture Behavioral of JK_FF_VHDL is temp <= '1';
signal temp: std_logic; elsif (J='1' and K='1') then
begin temp <= not (temp);
process (Clock)
end if;
begin
end if;
end process;
Output <= temp;
end Behavioral;
58
• Complete the following timing diagram for the flip-flop shown below.

59
T Flip-Flop
• T (Toggle) flip-flop
• Implementation of T Flip-Flops
• Conversion of J-K to T
• Connect the J and K inputs of a J-K flip-flop together
• Q+ = JQ′ + K′Q = TQ′ + T′Q

60
T Flip-Flop
• Implementation of T Flip-Flops
• Conversion of D to T
• Q+ = Q ⊕ T = TQ′ + T′Q

61
T Flip-Flop

62
63
 Flip-Flops with Additional Inputs
• Flip-flops often have additional inputs which can be used to set the flip-
flops to an initial state independent of the clock.
• Clear (Clr) and Preset (Pre) Input
• Clr and Pre are often referred to as asynchronous clear and preset inputs
because their operation does not depend on the clock.
• Clr will reset the flip-flop to Q = 0,
• Pre will set the flip-flop to Q = 1.

64
Flip-Flops with Additional Inputs
ClrN or PreN to
indicate active-
low clear and
preset inputs

65
 Flip-Flops with Additional Inputs
• The clear and preset inputs can also be synchronous, i.e., the clear and
set operations occur on the active edge of the clock.
• Often a synchronous clear or preset will override the other synchronous
inputs, e.g., a D flip-flop with a synchronous clear input will clear on the
active edge of the clock when the clear input is active independent of the
value on D.

66
 Flip-Flops with Additional Inputs
• D Flip-Flop with Clock Enable (D-CE)
• In synchronous digital systems, the flip-flops are usually driven by a
common clock so that all state changes occur at the same time in
response to the same clock edge.
• When designing such systems, we frequently encounter situations where
we want some flip-flops to hold existing data even though the data input
to the flip-flops may be changing.
• One way to do this is to gate the clock

67
 Flip-Flops with Additional Inputs
• D Flip-Flop with Clock Enable (D-CE)
• Gating the Clock:
• This method has two potential problems.
• First, gate delays may cause the clock to arrive at some flip-flops at
different times than at other flip-flops, resulting in a loss of
synchronization.
• Second, if En changes at the wrong time, the flip-flop may trigger due to
the change in En instead of due to the change in the clock, again resulting
in loss of synchronization.

68
 Flip-Flops with Additional Inputs
• D Flip-Flop with Clock Enable (D-CE)
• Rather than gating the clock, a better way is to use a flip-flop with a clock
enable (CE).
• A D flip-flop with a clock enable, which we will call a D-CE flip-flop.
• Q+ = Q·CE′ + D·CE

69
Excitation Table

70
• Complete the following timing diagram for a J-K flip-flop with a falling-
edge trigger and asynchronous ClrN and PreN inputs.

71
Asynchronous Sequential
Circuits
• The signals on the feedback loops in a sequential circuit define the
state of the circuit. In asynchronous sequential circuits the state of
the circuit can change whenever any input changes.
• E.g. Latch, a master-slave and edge-triggered flipflop
• In order for asynchronous circuits to operate in a well defined
manner, they must satisfy several restrictions

72
Asynchronous Sequential
Circuits
• P+ = x′P + xQ
• Q+ = x′P′ + xQ
• Note that both equations contain static 1-
hazards.
• P+ contains a static 1-hazard for xPQ = 111 ↔
011.
• Figure shows next-state table with the stable
states circled.

73
 Asynchronous Sequential
Circuits
• Stable state xPQ = 111 and changing x to 0.
• The table indicates that the next state is PQ = 10
(i.e., P does not change and Q changes to 0).
• When x changes to 0, the output of Gate 2 changes
to 0 causing the outputs of both gates 4 and 5 to
change to 0.

74
Asynchronous Sequential
Circuits
• When the x inverter output changes to 1, P = 0
prevents the output of Gate 1 from changing to
1 so P remains 0; however, the output of Gate 3
changes to 1 and Q becomes 1.

75
Asynchronous Sequential
Circuits
• The circuit stabilizes in state PQ = 01. This
incorrect state transition is due to the static
1-hazard in P+, which causes a 0 glitch in P if
the x inverter delay is large and, because of
the feedback, P never changes back to 1.
• This problem can be eliminated by designing
the circuits to be free of hazards.
• Even if the circuit is free of hazards, delays in
the “wrong” places in the circuit can cause
incorrect state transitions.

76
 VARIOUS REPRESENTATIONS OF FLIP-FlOPS
• Characteristic Equations of Flip-flops
• The characteristic equations of flip-flops are useful in analyzing circuits made of them. Here, next
output Qn+1 is expressed as a function of present output Qn and input to flip-flops.

77
Introduction to Counter
• A counter driven by a clock can be used to count the number of clock cycles.
• Since the clock pulses occur at known intervals, the counter can be used as an
instrument for measuring time and therefore period or frequency.
• There are basically two different types of counters-synchronous and asynchronous.
• Serial, or asynchronous counter is defined as each flip-flop is triggered by the
previous flip-flop, and thus the counter has a cumulative settling time.
• An increase in speed of operation can be achieved by use of a parallel or
synchronous counter. Here, every flip-flop is triggered by the clock (in
synchronism), and thus settling time is simply equal to the delay time of a single
flip-flop.
• Serial and parallel counters are used in combination to compromise between
speed of operation and hardware count. 78
 ASYNCHRONOUS COUNTERS-1
• The term asynchronous refers to events that do not have a fixed time relationship with each other and, generally, do not
occur at the same time.
• An asynchronous counter is one in which the flip-flops (FF) within the counter do not change states at exactly the same time
because they do not have a common clock pulse.
• The clock input of an asynchronous counter is always connected only to the LSB flip-flop.
• A 2-Bit Asynchronous Binary Counter
• Figure shows a 2-bit counter connected for asynchronous operation. Notice that the clock (CLK) is applied to the clock input
(C) of only the first flop-flop, FF0, which is always the least significant bit (LSB). The second flip-flop, FF1, is triggered by the
out-put of FF0. FF0 changes state at the positive-going edge of each clock pulse, but FF1 changes only when triggered by a
negative-going transition of the Q0 output of FF0.

79
ASYNCHRONOUS COUNTERS-2
• Ripple Counters (Up Counter)
• Figure shows (Next slide) three negative edge- triggered, JK flip-flops connected in
cascade.
• The system clock, a square wave, drives flip-flop A. The output of A drives B, and the
output of B drives flip-flop C. All the J and K inputs are tied to +VCC· This means that
each flip-flop will change state (toggle) with a negative transition at its clock input.
• When the output of a flip-flop is used as the clock input for the next flip-flop, we
call the counter a ripple counter, or asynchronous counter.
• The A flip-flop must change state before it can trigger the B flip-flop, and the B flip-
flop has to change state before it can trigger the C flip-flop.
• If each flip-flop in this three-flip-flop counter has a propagation delay time of 10 ns,
the overall propagation delay time for the counter is 30 ns.
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ASYNCHRONOUS COUNTERS-3

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ASYNCHRONOUS COUNTERS-4
• The waveform at the output of flip-flop A is one-half the clock frequency.
• The waveform at the output of flip-flop B is one-half the frequency of A
and one-fourth the clock frequency.
• The frequency of the waveform at C is one-half that at B, but it is only
one-eighth the clock frequency.
• What is the clock frequency, if the period of the waveform at C is 24 μs?
• Since there are eight clock cycles in one cycle of C, the period of the clock
must be 24/8 = 3 μs. The clock frequency must then be l/(3 x 10-6) = 333
kHz.

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ASYNCHRONOUS COUNTERS-5
• A binary ripple counter counts in a straight binary sequence, a counter having n flip-flops will have 2n
output conditions.
• For instance, the three-flip-flop counter just discussed has 2 3 = 8 output conditions (000 through 111).
Five flip-flops would have 25 = 32 output conditions (00000 through 11111 ), and so on.
• The largest binary number that can be represented by n cascaded flip-flops has a decimal equivalent of
2n-1.
• For example, the three-flip-flop counter reaches a maximum decimal number of 2 3- 1.
• The maximum decimal number for five flip-flops is 2 5 - l = 31, while six flip-flops have a maximum count
of 63.
• A three-flip-flop counter is often referred to as a modulus-8 (or mod-8) counter since it has eight states.
Similarly, a four-flip-flop counter is a mod-16 counter, and a six-flip-flop counter is a mod-64 counter.
• The modulus of a counter is the total number of states through which the counter can progress.

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ASYNCHRONOUS COUNTERS-6
• How many flip-flops are required to construct a mod-128 counter? A
mod-32? What is the largest decimal number that can be stored in a
mod-64 counter?
• A mod-128 counter must have seven flip-flols, since 27 = 128.
• Five flip-flops are needed to construct a mod-32 counter.
• The largest decima1 number that can be stored in a six-flop flip
counter (mod-64) is 111111 = 63.
• Note carefully the difference between the modulus ( total number of
states) and the maximum decimal number.

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ASYNCHRONOUS COUNTERS-8
• Example

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 ASYNCHRONOUS COUNTERS-9
• Ripple Counters (Down Counter)
• In 3-bit ripple up counter the system clock is still used at the clock input to flip-flop A, but the
complement of A, A’, is used to drive flip-flop B, likewise; B’ is used to drive flip-flop C.

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ASYNCHRONOUS COUNTERS-10
• Ripple Counters (4-bit Down Counter)

87
DECADE COUNTERS-1
• A Mod-5 Counter

88
DECADE COUNTERS-2
• A Mod-5 Counter
• A modulo – 5 counter, the counter should reset when it reaches state
101.
• The inputs to the NAND gate should be connected to the outputs Q1
and Q3.
• When the output of both these stages attains 1, then the output of
the NAND gate is 0 and this resets the counter.

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DECADE COUNTERS-3
• A Mod-12 Counter

90
DECADE COUNTERS-4
• Lab Experiment: The 7490 In Lab We Use
this Table

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DECADE COUNTERS-5
• Lab Experiment: The 7490
• MOD-10 Counter CLK +5V

Output
Clock
QD QC QB QA 14,INPUT A 05,VCC 01,INPUT B 12 QA
0 0 0 0 0
1 0 0 0 1 09 QB
06, Rq1 IC 7490
2 0 0 1 0 DECADE COUNTER 08 QC
3 0 0 1 1 07, RO1
4 0 1 0 0 11 QD
5 0 1 0 1 10,GND
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1

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DECADE COUNTERS-6
• Lab Experiment: The 7490
• MOD-8 Counter
CLK +5V

Output
Clock
QD QC QB QA 14,INPUT A 05,VCC 01,INPUT B 12 QA
0 0 0 0 0
1 0 0 0 1 09 QB
06,Rq1 IC 7490
2 0 0 1 0 DECADE COUNTER
07,Rq2 08 QC
3 0 0 1 1
4 0 1 0 0 11 QD
5 0 1 0 1 10,GND 02,R1 03,R2
6 0 1 1 0
7 0 1 1 1

93