Circuit Design with Logic

Gates
Logic Gates
• Logic gates are the basic building blocks of any digital
system.
• It is an electronic circuit having one or more than one input
and only one output.
• The relationship between the input and the output is based
on a certain logic. Based on this, logic gates are named as
AND gate, OR gate, NOT gate etc.
• Most electronic devices we use today will have some form
of logic gates in them. For example, logic gates can be used
in technologies such as smartphones, tablets or within
memory devices.
Logic Gates
• At any one time, a digital device will be in one of these
two binary situations.
• A light bulb can be used to demonstrate the operation of a
logic gate.
• When logic 0 is supplied to the switch, it is turned off, and
the bulb does not light up.
• The switch is in an ON state when logic 1 is applied, and
the bulb would light up.
• In integrated circuits (IC), logic gates are widely
employed..
 A Simple Circuit

A X
A X
(input) (output) 0 0

1 1
X A
AND Gate
• An AND gate has a single output and two or more inputs.
• When all of the inputs are 1, the output of this gate is 1.
• The AND gate’s Boolean logic is Y=A.B if there are two inputs A and
B.
• Therefore, in And gate, the output is high when all the inputs are high.
A
X
A B X
B
0 0 0
0 1 0
X  A.B 1 0 0
1 1 1
OR Gate
• Two or more inputs and one output can be used in an OR gate.
• The logic of this gate is that if at least one of the inputs is 1, the output
will be 1.
• The OR gate’s output will be given by the following mathematical
procedure if there are two inputs A and B: Y=A+B
• Therefore, in the OR gate the output is high when any of the inputs is
high.
A B X
A 0 0 0
X
B 0 1 1
1 0 1
X A  B 1 1 1
NOT Gate
• NOT gate is also known as Inverter. It has one input A and one
output Y.
• The NOT gate is a basic one-input, one-output gate.
• When the input is 1, the output is 0 and vice versa. A NOT gate is
sometimes called as an inverter because of its feature.
• If there is only one input A, the output may be calculated using the
Boolean equation Y=A’.
• A NOT gate, as its truth table shows, reverses the input signal.

A X
A X
0 1
X A 1 0
NAND Gate
• A NAND gate, sometimes known as a ‘NOT-AND’ gate, is essentially a Not
gate followed by an AND gate.
• This gate’s output is 1 only if none of the inputs is 1. Alternatively, when all
of the inputs are not high and at least one is low, the output is high.
• If there are two inputs A and B, the Boolean expression for the NAND gate is
Y=(A.B)’
• The NAND gate is known as a universal gate because it may be used to
implement the AND, OR, and NOT gates.
A B X
A 0 0 1
X
0 1 1
B
1 0 1
X  A.B 1 1 0
NOR Gate
• A NOR gate, sometimes known as a “NOT-OR” gate, consists of an
OR gate followed by a NOT gate.
• This gate’s output is 1 only when all of its inputs are 0. Alternatively,
when all of the inputs are low, the output is high.
• The Boolean statement for the NOR gate is Y=(A+B)’ if there are two
inputs A and B.
• The NOR gate is sometimes known as a universal gate since it may be
used to implement the OR, AND, and NOT gates. A B X

A 0 0 1
X 0 1 0
B
1 0 0

X A  B 1 1 0
 XOR (eXclusive OR) Gate
• XOR or Ex-OR gate is a special type of gate. It can be used in the half
adder, full adder and subtractor. The exclusive-OR gate is abbreviated
as EX-OR gate or sometime as X-OR gate. It has n input (n >= 2) and
one output.
• The Exclusive-OR or ‘Ex-OR’ gate is a digital logic gate that accepts
more than two inputs but only outputs one value.
• If any of the inputs is ‘High,’ the output of the XOR Gate is ‘High.’ If
both inputs are ‘High,’ the output is ‘Low.’ If both inputs are ‘Low,’
the output is ‘Low.’
• The Boolean equation for the XOR gate is Y=A’.B+A.B’ if there are
two inputs A and B. A B X
0 0 0
A
X 0 1 1
B
1 0 1
X A  B
XOR (eXclusive OR) Gate
XNOR Gate
• XNOR gate is a special type of gate. It can be used in the half adder,
full adder and subtractor. The exclusive-NOR gate is abbreviated as
EX-NOR gate or sometime as X-NOR gate. It has n input (n >= 2) and
one output. The XNOR gate is the complement of the XOR gate.
• The Exclusive-NOR or ‘EX-NOR’ gate is a digital logic gate that
accepts more than two inputs but only outputs one.
• If both inputs are ‘High,’ the output of the XNOR Gate is ‘High.’ If
both inputs are ‘Low,’ the output is ‘Low.’ If one of the inputs is
‘Low,’ the output is ‘Low.’
• If there are two inputs A and B, then the XNOR gate’s Boolean
equation is: Y=A.B+A’B’. A B X

A 0 0 1
X
B 0 1 0
1 0 0
X A  B 1 1 1
XNOR Gate
• Uses of Logic Gates
• Logic gates are utilized in a variety of technologies. These are
components of chips (ICs), which are components of computers, phones,
laptops, and other electronic devices.
• Logic gates may be combined in a variety of ways, and a million of
these combinations are necessary to make the newest gadgets, satellites,
and even robots.
• Simple logic gate combinations can also be found in alarms, buzzers,
switches, and street lights. Because these gates can make a choice to
start or stop based on logic, they are often used in a variety of sectors.
• Logic gates are also important in data transport, calculation, and data
processing. Even transistor-transistor logic and CMOS circuitry make
extensive use of logic gates.
 Boolean Algebra
• The logical symbol 0 and 1 are used for representing the digital input or output.
• The symbols "1" and "0" can also be used for a permanently open and closed
digital circuit.
• The digital circuit can be made up of several logic gates.
• To perform the logical operation with minimum logic gates, a set of rules were
invented, known as the Laws of Boolean Algebra.
• These rules are used to reduce the number of logic gates for performing logic
operations.
• The Boolean algebra is mainly used for simplifying and analyzing the complex
Boolean expression.
• It is also known as Binary algebra because we only use binary numbers in this.
• George Boole developed the binary algebra in 1854.
 Rules of Boolean Algebra
• Variable used can have only two values. Binary 1 for HIGH and
Binary 0 for LOW.
• Complement of a variable is represented by an overbar (-). Thus,
complement of variable B is represented as thus if B = 0 then =1
and B = 1 then = 0.
• ORing of the variables is represented by a plus (+) sign between them.
For example ORing of A, B, C is represented as A + B + C.
• Logical ANDing of the two or more variable is represented by writing
a dot between them such as A.B.C. Sometime the dot may be omitted
like ABC.
• There are six types of Boolean Laws.
 Boolean Algebra
• OR RULES ( ADDITION)

• 0+0=0
• 0+1=1
• 1+0=1
• 1+1=1
• A+0=A
• A+1=1
• A + A ( bar ) =1
 Boolean Algebra
• ​AND RULES (MULTIPLICATION)

• 0.0 = 0
• 0.1 = 0
• 1.0 = 0
• 1.1 = 1
• A.1 = A
• A.0 = 0
• A.A = A
• A.A ( bar ) = 0
 Commutative law
• Any binary operation which satisfies the following expression is
referred to as commutative operation.

• Commutative law states that changing the sequence of the variables

does not have any effect on the output of a logic circuit.
 Commutative Law
A
X
B
AB BA B
X
A

A
X
A  B B  A B
B
X
A
 Associative Law
This law states that the order in which the logic operations are
performed is irrelevant as their effect is the same.

B
X
C

A
X
B

C
 Distributive Law
This law allows us to open up of brackets. Simply, we can
open the brackets in the Boolean expressions.

A( B  C )  AB  AC
A  ( BC ) ( A  B ).( A  C )
 AND Law
These laws use the AND operation. Therefore they are called as AND laws.
 OR Law
These laws use the OR operation. Therefore they are called as OR laws.
 Null Law (AND)
A B X
A
X=0 0 0 0
B=0
0 1 0

A.0 0 1 0 0

1 1 1
 Null Law (OR)
A B X
A
X=1 0 0 0
B=1
0 1 1

A  1 1 1 0 1

1 1 1
 Identity Law (AND)
A B X
A
X=A 0 0 0
B=1
0 1 0

A.1  A 1 0 0

1 1 1
 Identity Law (OR)
A B X
A
X=A 0 0 0
B=0
0 1 1

A  0 A 1 0 1

1 1 1
 Idempotent Law (AND)
A B X
A
X=A 0 0 0
B=A
0 1 0

A. A  A 1 0 0

1 1 1
 Idempotent Law (OR)
A B X
A
X=A 0 0 0
B=A
0 1 1

A  A A 1 0 1

1 1 1
 Inverse Law (AND)
A B X
A
X=0
B=A 0 0 0

0 1 0

A. A 0 1 0 0

1 1 1
 Inverse Law (OR)
A B X
A
X=1
B=A 0 0 0

0 1 1

A  A 1 1 0 1

1 1 1
 Absorption Law
• This law enables a reduction in a
complicated expression to a simpler one
by absorbing like terms.
A + (A.B) = A (OR Absorption Law)
A + AB
=A(1+B) → since 1 + B = 1
= A.1
=A
 Absorption Law
• A (A + B) = A
A (A + B) = A.A + A.B
= A+AB → since A . A = A
= A (1 + B)
= A.1
=A
 Absorption Law
• A + ĀB = A + B
A + ĀB = (A + Ā) (A + B) → since A+BC = (A+B)(A+C) using
distributive law
= 1 .(A + B) → since A + Ā = 1
=A + B

A . (Ā+B) = AB
=A . (Ā + B) = A. Ā + AB
= AB → since A Ā = 0
 Examples
• Derive the Boolean expression for the logic circuit
shown below:
 Examples
• Find the Boolean expression for the following system.
 Examples
• Find the Boolean expression for the following system.
 Examples
• Find the Boolean expression for the following system.
 Examples
• Find the Boolean expression for the following system.
 Examples
• Draw logic circuit based on following combination of gates for the expression :
• xy+xy’+y’z
• (A+B)(B+C)
• A’B+(B+C)’
• (AB+C)D
• (A’+B).(A+B’)
• A+BC+D’
• AB+(AC)’
 Examples
• Draw logic circuit based on following combination of gates for the expression :
• AB+(AC)’
 Examples
• Draw logic circuit based on following combination of gates for the expression :
• A + BC + D’
 DeMorgan’s Law
• A famous mathematician DeMorgan invented the
two most important theorems of boolean algebra.
• DeMorgan’s Theorems are two additional
simplification techniques that can be used to
simplify Boolean expressions. Again, the simpler
the Boolean expression, the simpler the resulting
logic.
 DeMorgan’s Law

AB  A  B A  B  AB

• Change the sign (AND to OR, OR to AND)

• Invert the individual terms
• Invert the whole expression
 DeMorgans Law (hints)
Use it:
• when you need to change the logical
operation (product-of-sums for example)
• to get rid of any nasty inversions
 DeMorgan’s Law Examples
• Example 1: (A.B.C)'
• (A.B.C)'=A'+B'+C'
• Example 2: (A+B+C)'
• (A+B+C)'=A'.B'.C’
DeMorgan’s Law Examples
 Different ways of representing a
Boolean function
• Different ways of representing a Boolean function is shown below.
• Sum-of-Products (SOP) Form
• Product-of-sums (POS) form
• Canonical forms
• There are two types of canonical forms:
• Sum-of-min terms or Canonical SOP
• Product-of- max terms or Canonical POS
 Sum of Product (SOP) Form
• The sum-of-products (SOP) form is a method (or form) of simplifying
the Boolean expressions of logic gates.
• In this SOP form of Boolean function representation, the variables are
operated by AND (product) to form a product term and all these
product terms are ORed (summed or added) together.
• Examples
• AB + ABC + CDE
 Product of Sums (POS) Form
• The product of sums form is a method (or form) of simplifying the
Boolean expressions of logic gates.
• In this POS form, all the variables are ORed, i.e. written as sums to
form sum terms.
• All these sum terms are ANDed (multiplied) together to get the
product-of-sum form. This form is exactly opposite to the SOP form
• Examples
• (A+B).(A + B + C).(C +D)
 Canonical Form (Standard
SOP and POS Form)
• Any Boolean function that is expressed as a sum of minterms or as a
product of max terms is said to be in its “canonical form”.
• It mainly involves in two Boolean terms, “minterms” and “maxterms”.
 Minterm
• Each of the product terms in the canonical SOP form is called a minterm.
• Minterm are represented as binary numbers in terms of 0s and 1s.
• The binary words are formed by representing each non-complemented variable
by 1 and each complemented variable by 0, and the decimal equivalent of this binary
word is represented as a subscript of m as m0, m1, m2, etc.
• We generally use the ∑ (sigma) notation to represent minterms.

Maxterm
• Each of the sum terms in the canonical POS form is called a maxterm.
• Maxterm can also be represented using binary numbers where each non-
complemented variable is represented using 0 and complemented variable using 1,
and the decimal equivalent of this binary word is represented as a subscript
of M as M0, M2, M2, etc.
• We generally use ∏ (pi) notation to represent the max terms.
• Note: For n-variable logic function there are 2n minterms and 2n maxterms.
 Minterm and Maxterm
• For instance, assume that we have two variables as a and b. After
performing AND operation, we call the Boolean product terms of
these two variables as min terms or standard product terms. These min
terms are a’b’, a’b, ba’ and ab.
• After performing OR operation, we call the Boolean product terms of
these two variables as max terms or standard sum terms. These max
terms are a+b, a+b’, a’+b and a’+b’.
• Min and Max terms for two literal binary expressions
 Minterm and Maxterm
• Min and Max terms for three literal binary expressions
 Minterm from values
• Using variable values, we can write the minterms as:
• If the variable value is 1, we will take the variable without its complement.
• If the variable value is 0, take its complement.
• Example
• Let's assume that we have three Boolean variables A, B, and C having values
• A=1
B=0
C=0
• Now, we will take the complement of the variables B and C because these values are
0 and will take A without complement. So, the minterm will be:
• Minterm=A.B'C'
• Let's take another example in which we have two variables B and C having the value
• B=0
C=1
• Minterm=B'C
 Shorthand notation for minterm
• We know that, when Boolean variables are in the form of minterm, the
variables will appear in the product. There are the following steps for
getting the shorthand notation for minterm.
• In the first step, we will write the term consisting of all the variables
• Next, we will write 0 in place of all the complement variables such as
~A or A'.
• We will write 1 in place of all the non-complement variables such as
A or b.
• Now, we will find the decimal number of the binary formed from the
above steps.
• In the end, we will write the decimal number as a subscript of
letter m(minterm). Let's take some example to understand the theory
of shorthand notation
 Shorthand notation for minterm
• Example 1: Minterm = AB'
• First, we will write the minterm:
Minterm = AB'
• Now, we will write 0 in place of complement variable B'.
Minterm = A0
• We will write 1 in place of non-complement variable A.
Minterm = 10
• The binary number of the minterm AB' is 10. The decimal point
number of (10)2 is 2. So, the shorthand notation of AB' is
Minterm = m2
 Shorthand notation for minterm
• Example 2: Minterm = AB'C'
• First, we will write the minterm:
Minterm = AB'C'
• Now, we will write 0 in place of complement variables B' and C'.
Minterm = A00
• We will write 1 in place of non-complement variable A.
Minterm = 100
• The binary number of the minterm AB'C' is 100. The decimal point
number of (100)2 is 4. So, the shorthand notation of AB'C' is
Minterm = m4
 Shorthand notation for maxterm
• We know that, when Boolean variables are in the form of maxterm,
the variables will appear in sum. The steps for the maxterm are same
as minterm:
• In the first step, we will write the term consisting of all the variables
• Next, we will write 0 in place of all the non complement variables
such as a or b.
• We will write 1 in place of all the complement variables such as ~A or
A'.
• Now, we will find the decimal number of the binary formed from the
above steps.
• In the end, we will write the decimal number as a subscript of letter
Here, M denotes maxterm.
 Shorthand notation for maxterm
• Example 1: Maxterm = A+B'
• First, we will write the minterm:
Maxterm = A+B'
• Now, we will write 0 in place of non complement variable A
• We will write 1 in place of complement variable B’.
• The binary number of the maxterm A+B' is 01. The decimal point
number of (01)2 is 1. So, the shorthand notation of A+B' is
Maxterm = M1
 Shorthand notation for maxterm
• Example 2: Maxterm = A+B'+C'
• First, we will write the maxterm:
Maxterm = A+B'+C'
• Now, we will write 0 in place of non complement variable A.
• We will write 1 in place of complement variable B’ and C’.
• The binary number of the maxterm A+B'+C' is 011. The decimal point
number of (011)2 is 3. So, the maxterm of A+B'+C' is M3.
 Example
• Express the following in corresponding minterm and maxterm
expression
Example
 K-MAP
• In many digital circuits and practical problems we need to find expression
with minimum variables.
• We can minimize Boolean expressions of 3, 4 variables very easily using K-
map without using any Boolean algebra theorems.
• K-map can take two forms Sum of Product (SOP) and Product of Sum (POS)
according to the need of problem.
• K-map is table like representation but it gives more information than TRUTH
TABLE. We fill grid of K-map with 0’s and 1’s then solve it by making
groups.
 K-MAP
• The K-map method is used for expressions containing 2, 3, 4,
and 5 variables.
• For a higher number of variables, there is another method used
for simplification called the Quine-McClusky method.
• In K-map, the number of cells is similar to the total number of
variable input combinations.
• For example, if the number of variables is three, the number of
cells is 23=8, and if the number of variables is four, the number
of cells is 24.
 Steps to solve expression using
K-map
• To minimize the given boolean function,
• We draw a K Map according to the number of variables it contains.
• We fill the K Map with 0’s and 1’s according to its function.
• Then, we minimize the function in accordance with the following
rules.
• Rule-01:
• We can either group 0’s with 0’s or 1’s with 1’s but we can not group
0’s and 1’s together.
• X representing don’t care can be grouped with 0’s as well as 1’s.
NOTE:There is no need of separately grouping X’s i.e. they can be
ignored if all 0’s and 1’s are already grouped.
 Steps to solve expression using
K-map
• Rule-02:
• Groups may overlap each other.
• Rule-03:
• We can only create a group whose number of cells can be represented in the
power of 2.
• In other words, a group can only contain 2n i.e. 1, 2, 4, 8, 16 and so on number
of cells.
• Example-
 Steps to solve expression using
K-map
• Rule-04:
• Groups can be only either horizontal or vertical.
• We can not create groups of diagonal or any other shape.
 Steps to solve expression using
K-map
• Rule-05:
• Each group should be as large as possible.
• Example
 Steps to solve expression using
K-map
• Rule-06:
• Opposite grouping and corner grouping are allowed.
• The example of opposite grouping is shown illustrated in Rule-05.
• The example of corner grouping is shown below.
• Example-
 Steps to solve expression using
K-map
• Rule-07:
• There should be as few groups as possible.

• From the groups made in previous step, find the product terms and sum them
up for SOP form.
 2 Variable K-map
• There is a total of 4 variables in a 2-variable K-map. There are two
variables in the 2-variable K-map.
• A general representation of a 2 variable K-map plot is shown below.

• When we are simplifying a Boolean equation using Karnaugh map, we

represent the each cell of K-map containing the conjunction term with 1.
After that, we group the adjacent cells with possible sizes as 2 or 4. In case
of larger k-maps, we can group the variables in larger sizes like 8 or 16.
2 Variable K-map
 2 Variable K-map
• Example:
F = X Y’ + X’ Y + X’Y’
• First, let’s construct the truth table for the given equation,
• We put 1 at the output terms given in equation.
 2 Variable K-map
• In this K-map, we can create 2 groups by following the
rules for grouping, one is by combining (X’, Y) and (X’,
Y’) terms and the other is by combining (X, Y’) and (X’,
Y’) terms.
• Here the lower right cell is used in both groups.
• After grouping the variables, the next step is determining
the minimized expression.
• By reducing each group, we obtain a conjunction of the
minimized expression such as by taking out the common
terms from two groups, i.e. X’ and Y’. So the reduced
equation will be X’ +Y’.
 3 Variable K-map
• The 3-variable K-map is represented as an array of eight
cells. In this case, we used A, B, and C for the variable.
• We can use any letter for the names of the variables.
• The binary values of variables A and B are along the left
side, and the values of C are across the top.
• The value of the given cell is the binary values of A and B
at left side in the same row combined with the value of C
at the top in the same column.
• For example, the cell in the upper left corner has a binary
value of 000, and the cell in the lower right corner has a
binary value of 101.
3 Variable K-map
 3 Variable K-map
• K map SOP for 3 variables

Z= ∑A,B,C(1,3,6,7)
 3 Variable K-map
• K map SOP for 3 variables

Z= ∑A,B,C(1,3,6,7)

• From the red group we get the product term,

 4 Variable K-map
• In the 4 variable k-map, 16 square are required. An
example of 4 variable k-map for SOP and POS form
are as follows: –
 Don't Care Condition
• The "Don't care" condition says that we can use the blank cells of a
K-map to make a group of the variables.
• To make a group of cells, we can use the "don't care" cells as either
0 or 1, and if required, we can also ignore that cell.
• We mainly use the "don't care" cell to make a large group of cells.
• The cross(×) symbol is used to represent the "don't care" cell in K-
map.
• don't care is state which is actually not mattered in certain
operation.
• For example you are writing then only your hands are used by
writing operation, legs are not. So you can move your legs but not
hands. So we can say that here don’t care condition is legs.
 Don't Care Condition
• We can change the standard SOP function into a POS expression by
making the "don't care" terms the same as they are.
• The missing minterms of the POS form are written as maxterms of the
POS form.
• In the same way, we can change the standard POS function into an
SOP expression by making the "don't care" terms the same as they are.
• The missing maxterms of the SOP form are written as minterm of the
SOP form.
Don't Care Condition – Examples
• Example 1: Minimize f = m(1,5,6,12,13,14) + d(4) in SOP minimal
form
• The k-map of the given function in the SOP form is as follows:

• So, the minimized SOP form of the function is:

• f = BC' + BD' + A'C'D
Don't Care Condition – Examples
• Minimize the following function in SOP minimal form using K-
Maps: F(A, B, C, D) = m(1, 2, 6, 7, 8, 13, 14, 15) + d(3, 5, 12)
• The SOP K-map for the given expression is:

• Therefore,
• f = AC'D' + A'D + A'C + AB
Classifications of Combinational and Sequential circuits
 Types of Sequential circuits

• The sequential circuits can be event driven, clock driven and pulse
driven. There are two main types of sequential circuits: (a)
Synchronous and (b) Asynchronous.
 Combinational Logic circuits
• The combinational logic circuits are the circuits that contain different
types of logic gates.
• Simply, a circuit in which different types of logic gates are combined
is known as a combinational logic circuit.
• There are the following characteristics of the combinational logic
circuit:
1. At any instant of time, the output of the combinational circuits
depends only on the present input terminals.
2. The combinational circuit doesn't have any backup or previous
memory. The present state of the circuit is not affected by the previous
state of the input.
3. The n number of inputs and m number of outputs are possible in
combinational logic circuits.
 Combinational Logic circuits

• The 'n' input variable comes from the external source while the 'm'
output variable goes to the external destination.
• In many applications, the source or destinations are storage registers.
 Half Adder
• An adder is a digital logic circuit in electronics that is extensively used for
the addition of numbers. In many computers and other types of processors,
adders are even used to calculate addresses and related activities and
calculate table indices in the ALU and even utilized in other parts of the
processors.
• The Half-Adder is a basic building block of adding two numbers as two
inputs and produce out two outputs.
• The adder is used to perform OR operation of two single bit binary
numbers.
• The augent and addent bits are two input states, and 'carry' and 'sum 'are
two output states of the half adder.
 Half Adder
LSB MSB

• Truth Table

• In the above table,

• 'A' and' B' are the input states, and 'sum' and 'carry' are the output states.
• The carry output is 0 in case where both the inputs are not 1.
• The least significant bit of the sum is defined by the 'sum' bit.
• The SOP form of the sum and carry are as follows:
• Sum = a‘b+ab'
Carry = ab
 Construction of Half Adder
Circuit:
• In the block diagram, we have seen that it contains two inputs and two
outputs.
• The augent and addent bits are the input states,
and carry and sum are the output states of the half adder.
• The half adder is designed with the help of the following two logic
gates:
• 2-input AND Gate.
• 2-input Exclusive-OR Gate or Ex-OR Gate
 2-input Exclusive-OR Gate or
Ex-OR Gate
• The Sum bit is generated with the help of the Exclusive-OR or Ex-
OR Gate.

• The above is the symbol of the EX-OR gate. In the above diagram, 'A'
and 'B' are the inputs, and the 'SUMOUT' is the final outcome after
performing the XOR operation of both numbers.
• The truth table of the EX-OR gate is as follows:
 2-input Exclusive-OR Gate or
Ex-OR Gate

• From the above table, it is clear that the XOR gate gives the result 1
when both of the inputs are different.
• When both of the inputs are the same, the XOR gives the result 0.
 2-input AND Gate:
• The XOR gate is unable to generate the carry bit. For this purpose, we
use another gate called AND Gate.
• The AND gate gives the correct result of the carry.

• The above is the symbol of the AND gate. In the above diagram, 'A'
and 'B' are the inputs, and 'OUT' is the final outcome after performing
AND operation of both numbers.
• There is the following truth table of AND Gate:
 2-input AND Gate:

• From the above table, it is clear that the AND gate gives the result 1
when both of the inputs are 1. When both of the inputs are different
and 0, the AND gates gives the result 0.
 Half-Adder logical circuit:
• So, the Half Adder is designed by combining the 'XOR' and 'AND' gates and
provide the sum and carry.

• There is the following Boolean expression of Half Adder circuit:

• Sum= A XOR B
• Carry= A AND B (A.B)
 Full Adder
• The half adder is used to add only two numbers.
• To overcome this problem, the full adder was developed.
• There are many situations where we need to add 3 bits for example,
• 111
• 1111
• +1101
• ______
• 11100
• Here after LSB we need to add 3 bits. So in this kind of requirement full adder
is used.
• The full adder is used to add three 1-bit binary numbers A, B, and carry C.
• The full adder has three input states and two output states i.e., sum and carry.
• Block diagram
 Full Adder
• Block diagram
 Full Adder
• Truth Table
 Full Adder
• Truth Table
• In the above table,
• 'A' and' B' are the input variables.
• These variables represent the two significant bits which are going to be added
• 'Cin' is the third input which represents the carry.
• From the previous lower significant position, the carry bit is fetched.
• The 'Sum' and 'Carry' are the output variables that define the output values.
• The eight rows under the input variable designate all possible combinations of
0 and 1 that can occur in these variables.
• Note: We can simplify each of the output 'Boolean function' with the help of
the unique map method.
 Full Adder

• No groups can be formed for Sum KMAP

• Sum = x' y' z+x' yz’+xy' z'+xyz = x XOR y XOR z
• In terms of a,b,c variable: a’b’c+a’bc’+ab’c’+abc = a XOR b XOR c
• 3 groups can be formed for carry KAMP
• Carry = xy+xz+yz = (x XOR y).z + xy
• In terms of a,b,c variable: (a XOR b).c + ab
• We can write this carry equation because carry is 1 when any two inputs are one. So in (x XOR
y).z +xy, when we keep any two values 1 we get answer 1. And this equation is also makes full
adder circuit easy.
 Construction of Full Adder
Circuit:

• The above block diagram describes the construction of the Full adder
circuit.
 Construction of Full Adder
Circuit:
• In the above circuit, there are two half adder circuits that are combined using
the OR gate.
• The first half adder has two single-bit binary inputs A and B. As we know
that, the half adder produces two outputs, i.e., Sum and Carry.
• The 'Sum' output of the first adder will be the first input of the second half
adder, and the 'Carry' output of the first adder will be the second input of the
second half adder.
• The second half adder will again provide 'Sum' and 'Carry'. The final outcome
of the Full adder circuit is the 'Sum' bit.
• In order to find the final output of the 'Carry', we provide the 'Carry' output of
the first and the second adder into the OR gate.
• The outcome of the OR gate will be the final carry out of the full adder circuit.
• The MSB is represented by the final 'Carry' bit.
 Construction of Full Adder
Circuit:
• The full adder logic circuit can be constructed using the 'AND' and the 'XOR'
gate with an OR gate.

A XOR B A XOR B XOR Cin

A.B (A XOR B).Cin

(A XOR B).Cin + AB

• The actual logic circuit of the full adder is shown in the above diagram. The
full adder circuit construction can also be represented in a Boolean expression.
 Construction of Full Adder
Circuit:
• Sum:
• Perform the XOR operation of input A and B.
• Perform the XOR operation of the outcome with carry. So, the sum is (A XOR
B) XOR Cin which is also represented as:
(A ⊕ B) ⊕ Cin
• Carry:
• Perform the 'AND' operation of input A and B.
• Perform the 'XOR' operation of input A and B.
• Perform the 'OR' operations of both the outputs that come from the previous
two steps. So the 'Carry' can be represented as:
A.B + (A ⊕ B).Cin
 Multiplexer
• A multiplexer is a combinational circuit that has 2n input lines and a single
output line.
• Simply, the multiplexer is a multi-input and single-output combinational circuit.
• A multiplexer is a combinational circuit that selects binary information from
one of many input lines and direct it to the single output line.
• The selection of the a particular output line is controlled by a set of selection
lines.
• Normally, there are 2n input lines and n selection lines whose combination
determine which line has to be selected.
• There are various types of the multiplexer which are as follows:
• 1) 2:1 MUX
• 2) 4:1 MUX
• 3) 8:1 MUX
• 4) 16:1 MUX
 Application of Multiplexers

MP3 Player

DVD Player

DTH Television
Play Station

0 0
• Here if both S1 and S0 are 0 0 then A0 input line will be selected and the data of
play station is transferred to the television.
 Application of Multiplexers
• Communication System
• By using a multiplexer, the efficiency of the communication system can be
increased by allowing the transmission of data, such as audio and video data from
different channels through single lines or cables.
• Computer Memory
• Multiplexers are used in computer memory to maintain a huge amount of
memory in the computers, and also to reduce the number of copper lines required
to connect the memory to other parts of the computer.
• Telephone Network
• In a telephone network, the multiple audio signals are brought into a single line
and transmitted with the implementation of MUX. By this way many audio
singles are isolated and ultimately receiver will receive the required audio signals.
• Transmission from the Computer System of a Satellite
• The multiplexer is used to transmit the data signals from the computer system of a
spacecraft or a satellite to the ground system by GPS.
 Advantages of Multiplexers
• Advantages
– Reduce number of wires
– Reduce circuit complexity and cost
– MUX can be used for the implementation of various circuits.
 2×1 Multiplexer:
• In 2×1 multiplexer, there are only two inputs, i.e., A 0 and A1, 1 selection line,
i.e., S0 and single outputs, i.e., Y.
• On the basis of the combination of inputs which are present at the selection
line S0, one of these 2 inputs will be connected to the output.
• The block diagram and the truth table of the 2×1 multiplexer are given below.
• Block Diagram:
 2×1 Multiplexer:
• Truth Table:

• The logical expression of the term Y is as follows:

• Y=S0'.A0+S0.A1
• Logical circuit of the above expression is given below:
 4×1 Multiplexer:
• In the 4×1 multiplexer, there is a total of four inputs, i.e., A 0, A1, A2, and A3, 2
selection lines, i.e., S0 and S1 and single output, i.e., Y.
• On the basis of the combination of inputs that are present at the selection lines
S0 and S1, one of these 4 inputs are connected to the output.
• The block diagram and the truth table of the 4×1 multiplexer are given below.
• Block Diagram:
 4×1 Multiplexer:
• Truth Table:

• The logical expression of the term Y is as follows:

• Y=S1' S0' A0+S1' S0 A1+S1 S0' A2+S1 S0 A3
• Logical circuit of the above expression is given below:
 8 to 1 Multiplexer
• In the 8 to 1 multiplexer, there are total eight inputs, i.e., A 0, A1, A2, A3, A4,
A5, A6, and A7, 3 selection lines, i.e., S0, S1and S2 and single output, i.e., Y.
• On the basis of the combination of inputs that are present at the selection lines
S0, S1, and S2, one of these 8 inputs are connected to the output.
• The block diagram and the truth table of the 8×1 multiplexer are given below.
• Block Diagram:
 8 to 1 Multiplexer
• Truth Table:

• The logical expression of the term Y is as follows:

• Y=S0'.S1'.S2'.A0+S0.S1'.S2'.A1+S0'.S1.S2'.A2+S0.S1.S2'.A3+S0'.S1'.S2 A4+S0.S1'.S2 A
5+S0'.S1.S2 .A6+S0.S1.S3.A7
 8 to 1 Multiplexer
• Logical circuit of the above expression is given below:
 16 to 1 Multiplexer
• In the 16 to 1 multiplexer, there are total of 16 inputs, i.e., A 0, A1, …, A16, 4
selection lines, i.e., S0, S1, S2, and S3 and single output, i.e., Y.
• On the basis of the combination of inputs that are present at the selection lines
S0, S1, and S2, one of these 16 inputs will be connected to the output.
• The block diagram and the truth table of the 16×1
 16 to 1 Multiplexer
• Truth Table:
 16 to 1 Multiplexer
• The logical expression of the term Y is as follows:
• Y=A0.S0'.S1'.S2'.S3'+A1.S0'.S1'.S2 '.S3+A2.S0'.S1'.S2.S3'+A3.S0'.S1 '.S2.S3+A4.S0'.S1.
S2'.S3'+A5.S0 '.S1.S2'.S3+A6.S1.S2.S3'+A7.S0 '.S1.S2.S3+A8.S0.S1'.S2'.S3'+A9 .S0.S1'.
S2'.S3+Y10.S0.S1'.S2.S3 '+A11.S0.S1'.S2.S3+A12
S0.S1.S2 '.S3'+A13.S0.S1.S2'.S3+A14.S0.S1 .S2.S3'+A15.S0.S1.S2'.S3
16 to 1 Multiplexer
 Decoder
• Decoder and Encoder both are multiple input and multiple output device.
• Decoder is a combinational circuit that converts N lines of input into 2N lines of
output.
• The binary information is passed in the form of N input lines.
• The output lines define the 2N-bit code for the binary information.
• N:2N , N number of lines can be the input and maximum 2N output we can get.
Output can be less than 2N but it can not be more than 2N .
• In simple words, the Decoder performs the reverse operation of the Encoder.
• The output of the decoder is nothing but the minterms of n input variable lines, when
it is enabled.
• Applications of Decoders are converting binary code into other codes like:
• Binary to Octal (input: 3 and output 23 = 8 as 8 is the base of octal, 3X8 Decoder)
• Binary to Hexadecimal (input: 4 and output 24 = 16 as 16 is the base of hexadecimal,
4X16 decoder)
• Binary to Decimal (input: 4 and output 24 = 16, 16 can be possible combinations can
be made but here required is only 10 as decimal base is 10. 4X10 decoder.)
 Application
• In digital electronic projects, the encoder and decoder play an important role.
• It is used to convert the data from one form to another form.
• Generally, these are frequently used in the communication systems like
telecommunication, networking, and transfer the data from one end to the
other end.
• In the same way, it is also used in the digital domain for easy transmission of
data, placed with the codes, and then transmitted.
• At the end of the receiver, the coded data are collected from the code and then
processed to display.
Application
Decoder
 2 to 4 line decoder:
• In the 2 to 4 line decoder, there is a total of three inputs, i.e., A 0, and A1 and E
and four outputs, i.e., Y0, Y1, Y2, and Y3.
• E stands for enabled pin and its value is always 1 then only circuit will work
and gives the output.
• For each combination of inputs, when the enable 'E' is set to 1, one of these
four outputs will be 1.
• The block diagram and the truth table of the 2 to 4 line decoder are given
below.
• Block Diagram:
 2 to 4 line decoder:
• Truth Table:

• The logical expression of the term Y0, Y1, Y2, and Y3 is as follows:
• Y3=E.A1.A0
Y2=E.A1.A0'
Y1=E.A1'.A0
Y0=E.A1'.A0'
 2 to 4 line decoder:
Y3=E.A1.A0
• Logical circuit of the above expressions is given below: Y2=E.A1.A0'
Y1=E.A1'.A0
Y0=E.A1'.A0'

Y1

Y2
 3 to 8 line decoder:
• The 3 to 8 line decoder is also known as Binary to Octal Decoder.
• In a 3 to 8 line decoder, there is a total of eight outputs, i.e., Y 0, Y1, Y2,
Y3, Y4, Y5, Y6, and Y7 and three inputs, i.e., A0, A1, and A2.
• This circuit has an enable input 'E'. Just like 2 to 4 line decoder, when
enable 'E' is set to 1, one of these outputs will be 1.
• The block diagram and the truth table of the 3 to 8 line encoder are
given below.
• Block Diagram:
 3 to 8 line decoder:
• Truth Table:

Y0=A0'.A1'.A2'
Y1=A0.A1'.A2'
Y2=A0'.A1.A2'
Y3=A0.A1.A2'
Y4=A0'.A1'.A2
Y5=A0.A1'.A2
Y6=A0'.A1.A2
Y7=A0.A1.A2
 3 to 8 line decoder:
• The logical expression and logic circuit of the term Y0, Y1, Y2, Y3, Y4,
Y5, Y6, and Y7 is as follows:
• Y0=A0'.A1'.A2'
Y1=A0.A1'.A2'
Y2=A0'.A1.A2'
Y3=A0.A1.A2'
Y4=A0'.A1'.A2
Y5=A0.A1'.A2
Y6=A0'.A1.A2
Y7=A0.A1.A2
 Encoders
• An Encoder is a combinational circuit that performs the reverse operation of
Decoder.
• It has maximum of 2n input lines and ‘n’ output lines.
• It will produce a binary code equivalent to the input, which is active High.
Therefore, the encoder encodes 2n input lines with ‘n’ bits.
• At any time, only one of these 4 inputs can be ‘1’ in order to get the respective
binary code at the output.
 4 to 2 line Encoder:
• In 4 to 2 line encoder, there are total of four inputs, i.e., Y 0, Y1, Y2, and Y3,
and two outputs, i.e., A0 and A1.
• In 4-input lines, one input-line is set to true at a time to get the respective
binary code in the output side.
• Below are the block diagram and the truth table of the 4 to 2 line encoder.
• Block Diagram:
 4 to 2 line Encoder:
• Truth Table:

• The logical expression of the term A0 and A1 is as follows:

A1 = Y3 + Y2
A0 = Y3 + Y1
 4 to 2 line Encoder:
• Logical circuit of the above expressions is given below:

A1 = Y3 + Y2
A0 = Y3 + Y1
 8 to 3 line Encoder:
• The 8 to 3 line Encoder is also known as Octal to Binary Encoder.
• In 8 to 3 line encoder, there is a total of eight inputs, i.e., Y 0, Y1, Y2, Y3, Y4,
Y5, Y6, and Y7 and three outputs, i.e., A0, A1, and A2.
• In 8-input lines, one input-line is set to true at a time to get the respective
binary code in the output side.
• Below are the block diagram and the truth table of the 8 to 3 line encoder.
• Block Diagram:
 8 to 3 line Encoder:
• Truth Table:

• The logical expression of the term A0, A1, and A2 are as follows:
A2 = Y7 + Y6 + Y5 + Y4
A1 = Y7 + Y6 + Y3 + Y2
A0 = Y7 + Y5 + Y3 + Y1
 8 to 3 line Encoder:
• A2 = Y7 + Y6 + Y5 + Y4
Logical circuit of the above expressions is given below:
A1 = Y7 + Y6 + Y3 + Y2
A0 = Y7 + Y5 + Y3 + Y1
 Introduction of Sequential Circuits
• Following figure shows combinational circuits. In combinational circuits
output depends on the present input only.
 Introduction of Sequential Circuits
• Sequential circuit is the combination of combinational circuits and memory.
• In sequential circuit present output depends on present input and past output.
• Example : flip flop, counter, register
• That means sequential circuits include memory elements that are capable of
storing binary information.
• Some sequential circuits may not contain combinational circuits, but only
memory elements.
 Flip Flop
• A flip flop is an electronic circuit with two stable states that can be used to
store binary data.
• The stored data can be changed by applying varying inputs.
• Flip-flops and latches are fundamental building blocks of digital electronics
systems used in computers, communications, and many other types of
systems.
• Both are used as data storage elements.
• It is the basic storage element in sequential logic. But first, let’s clarify the
difference between a latch and a flip-flop.
• The difference between a latch and a flip-flop is that a latch is level-triggered
(outputs can change as soon as the inputs changes) and Flip-Flop is edge-
triggered (only changes state when a control signal goes from high to low or
low to high).
 Flip Flop
• A circuit that has two stable states is treated as a flip flop.
• These stable states are used to store binary data that can be changed by
applying varying inputs.
• The flip flops are the fundamental building blocks of the digital system.
• Flip flops and latches are examples of data storage elements.
• In the sequential logical circuit, the flip flop is the basic storage element.
• The latches and flip flops are the basic storage elements but different in
working.
• Both latches and flip flops stores one bit of information that is (1 or 0)
 SR Flip Flop
• SR flip flop is the basic and simplest type of flip flop.
• It is a single bit storage element.
• It has only two logic gates.
• The output of each gate is connected to the input of another gate.
• The state of the SR flip flop is determined by the condition of the output Q.
• If its value is 1, then the state is said to be SET and if Q = 0, the state is said to
be RESET. Hence it is called SR flip flop.
• The SR flipflop can be constructed by using NAND gates or NOR gates.
 SR Flip Flop
• The S-R flip flop is the simplest and easiest circuit to understand.
• The SR flip flop is a 1-bit memory bistable device having two inputs, i.e., SET
and RESET. The SET input 'S' set the device or produce the output 1, and the
RESET input 'R' reset the device or produce the output 0. The SET and
RESET inputs are labeled as S and R, respectively.
• The SR flip flop stands for "Set-Reset" flip flop. The reset input is used to get
back the flip flop to its original state from the current state with an output 'Q'.
This output depends on the set and reset conditions, which is either at the logic
level "0" or "1".

• Truth Table:
 Kmap
• h
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