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COSC 403:
COMPUTER ARCHITECTURE
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ANNOUNCEMENTS!!! The HARVARD Architecture MODULE THREE HARVARD • The Harvard architecture is a computer architecture with a separate storage and signal pathways for instructions and data. It is often contrasted with the von Neumann architecture, where program instructions and data share the same memory and pathways. HARVARD (contd.) • The term is often stated as having originated from the Harvard Mark I relay-based computer, which stored instructions on punched tape (24 bits wide) and data in electro-mechanical counters. These early machines had data storage entirely contained within the central processing unit, and provided no access to the instruction storage as data. Programs needed to be loaded by an operator, the processor could not initialize itself.
[*] Copeland (2006). Von Neumann Architecture. p. 104
HARVARD (contd.)
[*] Copeland (2006). Von Neumann Architecture. p. 104
HARVARD AND JOHN VON NEUMANN • Harvard and von Neumann architectures are often portrayed as a dichotomy, but the various devices labeled as the former have far more in common with the latter than they do with each other. Harvard architecture was coined in the context of microcontroller design and only retrospectively applied to the Harvard machines and subsequently applied to RISC microprocessors with separated caches. [*] Copeland (2006). Von Neumann Architecture. p. 104 HARVARD AND JOHN VON NEUMANN • Modern processors appear to the user to be systems with von Neumann architecture, with the program code stored in the same main memory as the data. For performance reasons, internally and largely invisible to the user, most designs have separate processor caches for the instructions and data, with separate pathways into the processor for each. This is one form of what is known as the modified Harvard architecture. [*] Copeland (2006). Von Neumann Architecture. p. 104 HARVARD AND JOHN VON NEUMANN • In a system with a pure von Neumann architecture, instructions and data are stored in the same memory, so instructions are fetched over the same data path used to fetch data. This means that CPU cannot simultaneously read an instruction and read or write data from or to the memory. [*] Copeland (2006). Von Neumann Architecture. p. 104 HARVARD AND JOHN VON NEUMANN • In a computer using the Harvard architecture, the CPU can both read an instruction and perform a data memory access at the same time, even without cache. A Harvard architecture computer can thus be faster for a given circuit complexity because instruction fetches and data access do not contend for a single memory pathway. [*] Copeland (2006). Von Neumann Architecture. p. 104 HARVARD AND JOHN VON NEUMANN • Also, a Havard architecture machine has distinct code and data address spaces: instruction address zero is not the same as data address zero. Instruction address zero might identify a twenty- four bit value, while data address zero might indicate an eight-bit byte that is not part of that twenty-four-bit value. [*] Copeland (2006). Von Neumann Architecture. p. 104 MODIFIED HARVARD ARCHITECTURE • A modified Harvard architecture machine is very much like Harvard architecture machine, but it relaxes the strict separation between instruction and data while still letting the CPU concurrently access two (or more) memory buses. The most common modification includes separate instruction and data caches backed by a common address spaces. While the CPU executes from cache, it acts as a pure Harvard machine. When accessing backing memory, it acts like von Neumann machine (where code can be removed around like data, which is a powerful technique).
[*] Copeland (2006). Von Neumann Architecture. p. 104
MODIFIED HARVARD ARCHITECTURE
[*] Copeland (2006). Von Neumann Architecture. p. 104
N I O ST E U Q ? S Image Source: http://iamforkids.org/wp-content/uploads/2013/11/j04278101.jpg - Retrieved Online on January 11, 2016 ANNOUNCEMENTS!!! L E DU M O O F ND E
Compute's Amiga Machine Language Programming Guide (Daniel Wolf and Douglas Leavitt Jr. - 1988) (Programming Assembly Motorola 68000 68010 Commodore Amiga)