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Module 4

Uploaded by

Sarthak Anand
Copyright
© © All Rights Reserved
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EC203 Digital System Design

Module-4
(Sequential Circuits: Flip-flops, Registers, Counters, State Diagram)

Dr. S. Sengupta, ECE Dept. BIT Mesra


Y=1
Y’=0
Advantages of edge triggering:
FF change states only once for a clock cycle
Din 1 1 1 1

1 1 1 1
Q3

Q2 0 1 1 1

Q1 0 0 1 1

0 0 0 1
Q0
Application of Shift registers:

(1) Ring Counter


(2) Sequence generator
(3) Johnson Counter

[will be discussed later]


Counters
Basic Application of Counters
• A Counter is a device which stores (and sometimes displays) the
number of times a particular event or process has occurred, often in
relationship to a clock signal.

• Counters are used in digital electronics for counting purpose.

• For example, in UP counter a counter increases count for every rising/


falling edge of clock.

• A counter can follow the certain sequence based on our design like any
random sequence 0,1,3,2… .

• They are used as frequency dividers where the frequency of given


pulse waveform is divided.

• The main properties of a counter are timing , sequencing , and


Counters are broadly divided into two
categories

1. Asynchronous counter

2. Synchronous counter
1. Asynchronous Counter/ Ripple counter

In asynchronous counter we don’t use universal


clock, only first flip flop is driven by main clock and the clock
input of rest of the following flip flop is driven by output of
previous flip flops. or asynchronous counter

Counter pulse
or
clock pulse

[All FFs are –ve edge triggered]


Counting sequence
[All FFs are –ve edge triggered, i.e. o/p changes at the –ve edge of CLOCK PULSE]
Clock
No. of clock pulse 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

A1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

A2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0

A3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0

A4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0

Timing diagram of UP counter


Down counter
The previous counter was up-counter that counts in increasing order. For reverse
counting a down-counter is used [i.e. 15, 14, 13, 12,….]

Solution:
(1) Either, use +ve edge triggered FF and apply
normal output of the FF to clock input of next FF
[if normal output is not available]

(2) Or, keeping the –ve edge triggered FF as its,


apply the complemented output of the FF to clock
input of next FF
As per the second solution:
Timing diagram of DOWN counter
Design of MOD-N asynchronous counter

1) Modulus-N, N<2n, n= No. of FFs, counts from decimal 0-to-(N-1)


2) Connect as ripple counter
3) Find the binary of decimal-N
4) Connect all FF outputs that are 1 at the state of the number N as inputs to
an NAND gate
5) Connect the NAND gate output to the ‘clear’ input of all FFs
MOD-10 counter or BCD counter (asynchronous)

State of FFs:
Q3 Q2 Q1 Q0

Counter counts from 0-to-9, so total no. of count is 10, hence MOD-10
When the state after 1001 i.e. 1010 is about to come all FFs are cleared
so 1010 will not come
Hence, When Q3=1 and Q1=1, FFs are cleared
Circuit Diagram of MOD-10 counter or BCD counter (asynchronous)

Q3 Q2 Q1 Q0

𝒄𝒍𝒓 𝒄𝒍𝒓 𝒄𝒍𝒓 𝒄𝒍𝒓


Timing Diagram

glitches
(asynchronous)
Excitation table
(also
discussed later)
TA3

A3 A2

A’3
Propagation delay in synchronous counter
Design of sequential Circuits
Using
State Diagram
11
An example: state assignment
Unused-states

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