Lecture#2 1 Introduction To ESs
Lecture#2 1 Introduction To ESs
Chapter 1: Introduction
Mahmoud Masadeh 2
Fundamental rules
lens
• Common metrics
– Unit cost: the monetary cost of manufacturing each copy of the system,
excluding NRE cost
– NRE cost (Non-Recurring Engineering cost): The one-time
monetary cost of designing the system
– Size: the physical space required by the system
– Performance: the execution time or throughput of the system
– Power: the amount of power consumed by the system
– Flexibility: the ability to change the functionality of the system without
incurring heavy NRE cost
Time (months)
delayed entry
On-time triangle, representing market
Market rise Market fall penetration
Delayed – Triangle area equals revenue
• Loss
D W 2W
– The difference between the on-
On-time Delayed Time time and delayed triangle areas
entry entry
delayed entry
On-time
45 degrees (height is not W)
Market rise Market fall • Percentage revenue loss =
Delayed (D(3W-D)/2W2)*100%
• Try some examples
D W 2W – Lifetime 2W=52 wks, delay D=4 wks
On-time Delayed Time – (4*(3*26 –4)/2*26^2) = 22%
entry entry – Lifetime 2W=52 wks, delay D=10 wks
– (10*(3*26 –10)/2*26^2) = 50%
– Delays are costly!
• Costs:
– Unit cost: the monetary cost of manufacturing each copy of the system,
excluding NRE cost
– NRE cost (Non-Recurring Engineering cost): The one-time monetary cost of
designing the system
– total cost = NRE cost + unit cost * # of units
– per-product cost = total cost / # of units
= (NRE cost / # of units) + unit cost
• Example
– NRE=$2000, unit=$100
– For 10 units
– total cost = $2000 + 10*$100 = $3000
– per-product cost = $2000/10 + $100 = $300
$80,000 $80
$40,000 $40
$0 $0
0 800 1600 2400 0 800 1600 2400
Number of units (volume) Number of units (volume)
• Technology
– A manner of accomplishing a task, especially using
technical processes, methods, or knowledge
• Three key technologies for embedded systems
1. Processor technology
2. IC technology
3. Design technology
total = 0 total = 0
for i =1 to … for i =1 to …
General-purpose (“software”) Application-specific Single-purpose (“hardware”)
total = 0
for i = 1 to N loop
total += M[i]
end loop
Desired
functionality
Data
• Drawbacks memory
• Benefits total = 0
for i =1 to …
– Some flexibility, good performance, size and
power
• Drawbacks
– Large NRE cost to build the processor and compiler
• Application-specific instruction-set processor (ASIP) have two
well-known types:
– Microcontroller: Typically, monitor and set numerous single-bit control
signals but do not do large amount of data computation. Has simple
datapath
– Digital signal processors (DSPs): Do math intensive operations and
manipulate large array of data (digital signals)using one instruction
A=A+B[i]*C. It has a special purpose data-path
Human Hair
~75 m
. 0.18 m
180 nm
.
feature
General- Single-
purpose ASIP purpose
General, processor processor Customized,
providing improved: providing improved:
1983
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Embedded Systems Design: A Unified 42
Hardware/Software Introduction, (c) 2000 Vahid/Givargis
Moore’s law
• Wow
– This growth rate is hard to imagine, most people
underestimate
– How many ancestors do you have from 20 generations ago
• i.e., roughly how many people alive in the 1500’s did it take to make
you?
• 220 = more than 1 million people
– (This underestimation is the key to pyramid schemes!)
10,000 150,000,000
transistors transistors
Semiconductor Industry
Association
Embedded (SIA)
Systems Design: A Unified 11/28/202
Hardware/Software Introduction, (c) 2000 Vahid/Givargis 4
Design Technology
Test/Verification: Ensures
correct functionality at each
level, thus reducing costly Logic Logic Gates/ Gate
iterations between levels. specification synthesis Cells simulators
To final implementation
1. (Design) Verification
o Verifies correctness of design (target design errors)
o Performed by simulation, hardware emulation, or formal methods.
o Performed once prior to manufacturing
o Responsible for quality of design
2. (Manufacturing) Testing
o Verifies correctness of manufactured IC (target manufacturing defects)
o Two-part process:
• Test generation: software process executed once during design
• Test application: electrical tests applied to hardware
o Test application performed on every manufactured device
o Responsible for quality of devices
10,000
Productivity
100
10
0.1
0.01
2005
1993
2001
2003
1983
1987
1985
1991
1989
1981
1999
1997
1995
2007
2009
• Productivity measured as the number of transistors produced by
one designer in one month.
• Exponential increase over the past few decades
Embedded Systems Design: A Unified 56
Hardware/Software Introduction, (c) 2000 Vahid/Givargis
The co-design ladder
The choice of hardware versus software for a particular function is simply a tradeoff among various
design metrics, like performance, power, size, NRE cost, and especially flexibility; there is no
fundamental difference between what hardware or software can implement.
General- Single-
purpose ASIP purpose
General, processor processor Customized,
providing improved: providing improved:
1983
1985
1987
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Hardware/Software Introduction, (c) 2000 Vahid/Givargis
Design productivity gap
• 1981 leading edge chip required 100 designer months
– 10,000 transistors / 100 transistors/month
• 2002 leading edge chip requires 30,000 designer months
– 150,000,000 / 5000 transistors/month
• Designer cost increase from $1M to $300M
10,000 100,000
1,000 10,000
Logic transistors 100 1000
10 Gap 100 Productivity
per chip IC capacity
(in millions) 1 10 (K) Trans./Staff-Mo.
0.1 1
productivity
0.01 0.1
0.001 0.01
1981
1983
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1999
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The mythical man-month
• The situation is even worse than the productivity gap indicates
• In theory, adding designers to team reduces project completion time
• In reality, productivity per designer decreases due to complexities of team management
and communication
• In the software community, known as “the mythical man-month” (Brooks 1975)
• At some point, can actually lengthen project completion time! (“Too many cooks”)
Team
• 60000 15
1M transistors, 1 16 16
50000 19 18
designer=5000 trans/month
• 40000 23
Each additional designer 24
reduces for 100 trans/month 30000
Months until completion
• 20000 43
So 2 designers produce 4900 Individual
10000
trans/month each
0 10 20 30 40
Number of designers