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Lecture 3 TN213

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18 views

Lecture 3 TN213

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Layman 77
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© © All Rights Reserved
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TN 213 – ANALOG ELECTRONICS I

LECTURE 3

 BJT Small-Signal Analysis


 Common-Emitter Fixed-Bias
Configuration
 Voltage Divider Bias
BJT Small-Signal Analysis

 The transistor models introduced in previous lecture


will now be used to perform a small-signal ac analysis
of a number of standard transistor network
configurations.
 The networks analyzed represent the majority of those
appearing in practice today.
 Modifications of the standard configurations will be
relatively easy to examine once the content of this
lecture is reviewed and understood.
 Since the re model is sensitive to the actual point of
operation, it will be our primary model for the analysis
to be performed. For each configuration, however, the
effect of an output impedance is examined as provided
by the hoe parameter of the hybrid equivalent model.
Common-Emitter Fixed-Bias Configuration

 The first configuration to be analyzed in detail is the


common-emitter fixed-bias network.
Common-Emitter Fixed-Bias Configuration

 Note that the input signal Vi is applied to the base of


the transistor while the output Vo is off the collector.
 In addition, recognize that the input current Ii is not the
base current but the source current, while the output
current Io is the collector current.
 The small-signal ac analysis begins by removing the dc
effects of VCC and replacing the dc blocking capacitors
C1 and C2 by short-circuit equivalents, resulting in the
network of the following figure.
Common-Emitter Fixed-Bias Configuration

 Note that the common ground of the dc supply and the


transistor emitter terminal permits the relocation of RB
and RC in parallel with the input and output sections of
the transistor, respectively.
Common-Emitter Fixed-Bias Configuration

 In addition, note the placement of the important


network parameters Zi, Zo, Ii, and Io on the redrawn
network. Substituting the re model for the common-
emitter configuration will result in the network of the
figure below.
Common-Emitter Fixed-Bias Configuration

 The next step is to determine , re, and ro. The


magnitude of is typically obtained from a specification
sheet or by direct measurement using a curve tracer or
transistor testing instrument. The value of re must be
determined from a dc analysis of the system, and the
magnitude of ro is typically obtained from the
specification sheet or characteristics.
 Assuming that , re, and ro have been determined will
result in the following equations for the important two-
port characteristics of the system.

 Zi:
Common-Emitter Fixed-Bias Configuration

 For the majority of situations RB is greater than re by


more than a factor of 10 (recall from the analysis of
parallel elements that the total resistance of two
parallel resistors is always less than the smallest and
very close to the smallest if one is much larger than the
other), permitting the following approximation:
Common-Emitter Fixed-Bias Configuration

 Zo: Recall that the output impedance of any system is


defined as the impedance Zo determined when Vi = 0.
when Vi = 0, Ii = Ib = 0, resulting in an open-circuit
equivalence for the current source.
Common-Emitter Fixed-Bias Configuration
Common-Emitter Fixed-Bias Configuration
Common-Emitter Fixed-Bias Configuration

 Phase Relationship: The negative sign in the resulting


equation for Av reveals that a 180° phase shift occurs
between the input and output signals
Common-Emitter Fixed-Bias Configuration

 Example:
Common-Emitter Fixed-Bias Configuration
Common-Emitter Fixed-Bias Configuration
Voltage Divider Bias
 The next configuration to be analyzed is the voltage-
divider bias. Recall that the name of the configuration
is a result of the voltage-divider bias at the input side to
determine the dc level of VB.
Voltage Divider Bias

 Substituting the re equivalent circuit will result in the


network of the following figure. Note the absence of RE
due to the low-impedance shorting effect of the bypass
capacitor, CE.
Voltage Divider Bias
 VCC is set to zero, it places one end of R1 and RC at
ground potential as shown in the figure. In addition,
note that R1 and R2 remain part of the input circuit
while RC is part of the output circuit. The parallel
combination of R1 and R2 is defined by
Voltage Divider Bias
Voltage Divider Bias
Voltage Divider Bias
Voltage Divider Bias

 Example:
Voltage Divider Bias
Voltage Divider Bias
Voltage Divider Bias
SUMMARY

In this lecture we have dealt with


only two biasing methods, you
have to read chapter 8 of the book
for small signal analysis of other
biasing methods.

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