8257 DMA controller

What is DMAC ?

 DMA or Direct Memory Access Controller is an external device that controls the transfer of data

between I/O device and memory without the involvement of the processor.

 It holds the ability to directly access the main memory for read or write operation.

 Using a DMA controller, the device requests the CPU to hold its data, address and control bus,

so, the device is free to transfer data directly to/from the memory.

 The DMA data transfer is initiated only after receiving HLDA signal from the CPU.

 DMA controller was designed by Intel, to have the fastest data transfer rate with less processor

utilization.
 Why DMAC ?
Generally, to perform an operation, the microprocessor

first fetches the instruction -- then decodes it -- then further execute it.

But individually if the processor is performing all the task inside the system,

then it unnecessarily keeps the processor busy all the time.

So, to enhance the performance of the processor,

an external device is used that can manage data transfer operation

between peripherals and memory with least CPU utilization.

Basically, it is nothing but hardware-controlled data transfer, where the address and control

signals required for transferring the data is generated by an external device.

This method of data transfer is known as direct memory access and the external device

used for this purpose is known as DMA controller.

Need: We know that generally whenever there exists a need for transfer of data
between peripherals and main memory, then first the data is given to the processor
by the input device and then the processor further transfers the data to the
memory.

And at the time of data transfer operation, the processor cannot execute any other
operation.

Hence, if the system has a DMA controller, then it frees the CPU from data transfer
operation and at that particular time, the CPU can execute/ perform other
operations.
 Features of 8257

Here is a list of some of the prominent features of 8257 :

 It has four channels which can be used over four I/O devices.

 Each channel has 16-bit address and 14-bit counter.

 Each channel can transfer data up to 64kb. [since

 Each channel can be programmed independently.

 Each channel can perform read transfer, write transfer and verify transfer operations.

 It generates MARK signal to the peripheral device that 128 bytes have been transferred.

 It requires a single phase clock [all clock signals are effectively transmitted on 1 wire]

 Its frequency ranges from 250Hz to 3MHz.

 It operates in 2 modes, i.e., Master mode and Slave mode.

 8257 Architecture

The block diagram of

Pin diagram of 8257 DMA controller
 8257 Pin Description
DRQ0−DRQ3
These are the four individual channel DMA request inputs, which are used by the peripheral devices
for using DMA services.
When the fixed priority mode is selected, then DRQ0 has the highest priority and DRQ3 has the lowest
priority among them.
DACKo − DACK3
These are the active-low DMA acknowledge lines, which updates the requesting peripheral about the
status of their request by the CPU.
These lines can also act as strobe lines for the requesting devices.
Do − D7
These are bidirectional, data lines which are used to interface the system bus with the internal data
bus of DMA controller.
In the Slave mode, it carries command words to 8257 and status word from 8257.
In the master mode, these lines are used to send higher byte of the generated address to the latch.
IOR
It is an active-low bidirectional tri-state input line, which is used by the CPU to read internal
registers of 8257 in the Slave mode.
In master mode, it is used to read data from the peripheral devices during a memory write cycle.
IOW
It is an active low bi-direction tri-state line, which is used to load the contents of the data bus to the
8-bit mode register or upper/lower byte of a 16-bit DMA address register or terminal count register.
In master mode, it is used to load the data to the peripheral devices during DMA memory read
cycle.
CLK
It is a clock frequency signal which is required for the internal operation of 8257.
RESET
This signal is used to RESET the DMA controller by disabling all the DMA channels.
CS
It is an active-low chip select line.
In the Slave mode, it enables the read/write operations to/from 8257.
In the master mode, it disables the read/write operations to/from 8257.
Ao - A3
These are the four least significant address lines.
In slave mode, they act as an input, which selects one of the registers to be read or written.
In master mode, they are the four least significant memory address output lines generated by 8257.
A4 - A7
These are the higher nibble of the lower byte address generated by DMA in the master mode.
READY
It is an active-high asynchronous input signal, which makes DMA ready by inserting wait states.
HRQ
This signal is used to receive the hold request signal from the output device.
In the slave mode, it is connected with a DRQ input line 8257.
In Master mode, it is connected with HOLD input of the CPU.
HLDA
It is the hold acknowledgement signal which indicates the DMA controller that the bus has
been granted to the requesting peripheral by the CPU when it is set to 1.
MEMR
It is the low memory read signal, which is used to read the data from the addressed memory
locations during DMA read cycles.
MEMW
It is the active-low three state signal which is used to write the data to the addressed memory location
during DMA write operation.
ADST
This signal is used to convert the higher byte of the memory address generated by the DMA controller into
the latches.
AEN
This signal is used to disable the address bus/data bus.
TC
It stands for ‘Terminal Count’, which indicates the present DMA cycle to the present peripheral devices.
MARK

The mark will be activated after each 128 cycles or integral multiples of it from the beginning. It indicates

the current DMA cycle is the 128th cycle since the previous MARK output to the selected peripheral

device.

Vcc

It is the power signal which is required for the operation of the circuit.
 Operation of DMA Controller
 Basically, whenever an I/O device needs to transfer the data to the memory, then it initially sends a

DMA request (DRQ) to DMA controller.

 On receiving data transfer request, the DMA controller sends Hold request (HRQ) to the CPU and

waits for the CPU to assert the HLDA - hold acknowledge by the CPU.

 So, on getting HRQ request by the controller, the CPU leaves the control over all the buses (i.e., tri-

state’s the data, control and address bus) and acknowledges the HRQ request by sending HLDA to

the controller.

 Now the CPU is in HOLD state and the DMAC has to manage the operations over buses.

 The processor is free from any data transfer operation until an interrupt is generated by the DMAC

controller about the completion of the transfer.

The figure below represents a system having a DMA controller:
 Basic functioning of the DMAC inside the system.

DMAC inside the system can be either in an idle and active state.

In the idle cycle, initially when the system gets on, the processor has control over the system buses and the

switches are connected to the ‘X’ position.

In this position, the buses form the connection between main memory and peripherals through the processor. So,

in this position, the processor performs the execution of the instruction.

But once, need arises to read/write the data from /to the disk.

Then the microprocessor sends an instruction to the disk controller about the read/write operation of the data.

On fetching the required data, the disk controller (peripheral device) sends DMA request, i.e., DRQ signal to the

DMAC.

This DRQ signal indicates that the device directly wants to transfer data to the memory without disturbing the

processor.
So, on receiving the DRQ signal, HRQ signal is sent by the DMA controller (HOLD request ) to the

microprocessor.

The HRQ signal shows the interest of the DMAC to have access to system buses.

So, on receiving HRQ, the CPU tri-states its buses to grant the control to the DMAC.

Once the processor frees the buses, then it sends the HLDA signal to the DMA controller.

And on receiving HLDA signal, the control over the buses is given to the DMA controller and the switch

position now changes from X to Y.

So, gaining control over the buses, the active cycle of the DMA gets enabled.

Thus, it sends the acknowledge signal DACK to the disk controller that shows that it is now ready for the

transfer of data.
After acknowledging the disk controller, the DMAC loads the control signal over the bus according to the

operation that is to be performed.

In case of a write operation, IOR’ and MEMW’ signals are loaded.

When IOR signal is received by the disk controller then it loads the required data into the data bus.

Also, MEMW’ signal shows the presence of address on the address bus where the data is to be

transferred.

Thus, the disk controller can directly transfer the data to the desired memory location without the CPU.

Once the data transfer is accomplished then the DMA controller generates an interrupt by varying switch

position from Y to again X.

This indicates the microprocessor about the completion of the data transfer operation.

So, by this, the control of the buses is again transferred to the processor, and it starts executing the

further operation.
Modes of DMA Transfer:
During the DMA Transfer CPU can perform only those operation in which it doesn’t require the access of System Bus which
means mostly CPU will be in blocked (idle) state.
•For how much time CPU remains in the blocked state or we can say for how much time CPU will give the control of DMAC
of system buses will actually depend upon the following modes of DMA Transfer and after that CPU will take back control
of system buses from DMAC.
•DMA controller has four modes for data transfer:

Mode-1: Block Transfer Mode.

•In this mode, the DMAC is programmed to transfer all the bytes in one complete DMA operation.
• After a byte is transferred, the CAR and CWCR are adjusted accordingly.
•The system bus is returned to the µP, only after all the bytes are transferred. i.e. TC is reached or EOP signal is issued.
• It is the fastest form of DMA but keeps the microprocessor inactive for a long time.
•The DREQ signal needs to be active only in the beginning for requesting the DMA service initially.
• Thereafter DREQ can become low during the transfer.
Mode 2 - Single Byte Transfer Mode/ Cycle Stealing
•Once the DMAC becomes the bus master, it will transfer only ONE BYTE and return the bus back to the
microprocessor.
•As soon as the microprocessor performs one bus cycle, DMAC will once again take the bus back from
the microprocessor.
•Both DMAC and microprocessor are constantly stealing bus cycles from each other.
• It is the most popular method of DMA, because it keeps the microprocessor active in the background.
• After a byte is transferred, the CAR and CWCR are adjusted accordingly.
•The system bus is returned to the µP.
• For further bytes to be transferred, the DREQ line must go active again, and then the entire operation is
repeated.
Mode 3- Demand Transfer Mode
•It is very similar to Block Transfer, except that the DREQ must active throughout the DMA operation.
•If during the operation DREQ goes low, the DMA operation is stopped and the busses are returned to
the µP.
•In the meantime, the µP can continue with its own operations. Once DREQ goes high again, the DMA
operation continues from where it had stopped.

Mode 4 - Cascade Transfer Mode

• In this mode, more than one DMACs are cascaded together.
• It is used to increase the number of devices interfaced to the µP. Here we have one
Master DMAC, to which one or more Slave DMACs are connected.
•The Slave gives HRQ to the Master on the DREQ of the Master, and the Master gives
HRQ to the µP on the HOLD of the µP.
Cascade Mode – In this multiple channels are used, we can further cascade more number of DMACs.

Advantages:
Improved performance: DMA improves system performance by
freeing up the CPU to perform other tasks while data is being
transferred between memory and I/O devices. This allows for faster
Disadvantages: and more efficient data transfer.
Complexity: DMA requires specialized hardware and software to
function, which can add to the complexity of a system. This can Reduced CPU overhead: With DMA, the CPU is not required to be
make it difficult to implement and troubleshoot. involved in data transfer, which reduces the CPU overhead and
Security risks: DMA can be a security risk if not properly allows it to focus on other tasks. This is particularly useful in real-
configured or secured. Hackers can exploit vulnerabilities in DMA time systems where low latency and fast response times are
to gain unauthorized access to a computer system or steal data. important.
Limited control: Since the CPU is not involved in data transfer
with DMA, it has limited control over the transfer process. This Support for high-bandwidth devices: DMA can support high-
can lead to data corruption or errors if the transfer process is not bandwidth devices such as graphics cards and network interfaces
properly managed. that require fast data transfer rates.
Resource conflicts: DMA can lead to resource conflicts if multiple
devices attempt to access memory simultaneously. This can Efficient use of system resources: DMA allows multiple devices to
cause system instability and performance issues if not properly access memory simultaneously, which makes more efficient use of
Operating Modes of 8257:

The Operating Modes of 8257 can be programmed to operate in following modes :

Rotating Priority Mode :

In this mode, the priority of the channels has a circular sequence. The channel
being serviced gets the lowest priority and the channel next to it gets the
highest priority as shown
Thus, with rotating priority in a single chip DMA system, any device requesting
service is guaranteed to be recognized after no more than three higher priority
services have occurred. This prevents any one channel from monopolizing the
system. The rotating priority mode can be set by writing logic ‘1’ in the bit 4 of
the mode set register.

Fixed Priority Mode :

In the fixed priority, channel 0 has the highest priority and channel 3 has the
lowest priority..
In the fixed priority, after recognition of any one channel for service, the other
channels are prevented from interfering with that service until it is completed. If
bit 4 of mode set register is logic 0, 8257 operates in fixed priority mode.
Extended Write Mode :
Microcomputer systems allow use of various types of memory and I/O devices with different access time.
If a device can not be accessed within a specific amount of time it returns a “not ready” indication to the 8257 that causes the 8257 to
insert one or more wait states in its internal sequencing.
The extended write option provides alternative timing for the I/O and memory write signals which allows the devices to return an early
READY and prevents the unnecessary occurrence of wait states in the Operating Modes of 8257.
It does this by activating MEMW and IOW signals earlier in the DMA cycle, giving more setup time.

TC STOP Mode :
If the TC stop bit is set, a channel is disabled (i.e. its enable bit is reset) after the terminal count (TC) output goes high, thus
automatically preventing further DMA operation on that channel.
To enable DMA operation on the channel it is necessary to set enable bit of the corresponding channel in the mode set register.
If the TC STOP bit is not set, the occurrence of the TC output has no effect on the channel enable bits.
Auto Load Mode :
Auto load Mode when enabled, permits block chaining operations, without immediate software intervention between blocks.

In this mode, channel 2 parameters (DMA starting address, terminal count and DMA transfer mode) are initialized as usual for the first

data block.

These parameters are automatically duplicated in the channel 3 registers when channel 2 is initialized.

After the first block of DMA cycles is executed by channel 2 (i.e., after the TC output goes high), the parameters stored in the channel 3

registers are transferred to channel 2 during an ‘update’ cycle and next block of DMA cycle is executed.

This repeat block operations can be used in applications such as CRT refreshing. During the update cycle, it is necessary to prevent the

CPU from inadvertently skipping a data block by overwriting a starting address or terminal count in the channel 3 registers before those

parameters are properly auto-loaded into channel 2.

DMA Cycles:

DMA READ : In this cycle, data is transferred from memory to I/O device.

DMA Write : In this cycle, data is transferred from I/O device to memory.

DMA Verify : In this cycle, data is not transferred between memory and I/O.

It is used by the, peripheral device to verify the data that has been recently transferred.
Status Register: It is an 8-bit register that indicates which channel is currently under DMA services or
which channels has reached its terminal count.
It basically gives the status of the channels.
The terminal counts(TC) bits indicates if the channel has reached its terminal count.
If terminal count is reached, the transfers are terminated.
Mode Register: It is an 8 bit register that determines the operating mode, i.e., the transfer mode and other
transfer parameters, for a channel. Each channel has its own mode register which is selected by bit
positions 0 and 1.