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Analysis of Asynchronous Sequential Circuit (1)

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32 views

Analysis of Asynchronous Sequential Circuit (1)

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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Analysis of Asynchronous

Sequential
Circuits

K.PRAVEEN
A.P(Sr.Gr)/DECE, CEG
Agenda of this Presentation
• Definition & Analysis of
Asynchronous Sequential Circuits
• Transition Table
• Flow Table
• Race Condition
• Race Free State Assignment
• Hazards

2
Asynch. vs. Synch.
 Asynchronous circuits don’t use
clock pulses
 State transitions by changes in inputs
 Storage Elements:
 Clockless storage elements or
 Delay elements
 In many cases, as combinational
feedback
 Normally much harder to design

3
Asynch. Sequential Circuit
x1 z1
x2 z2
inputs outputs
Combinational
xn zm
Circuit
y1 Y1
Next
Current y2 Y2
State
State yk Yk

delay

delay

delay

4
Asynch. Sequential Circuit
 yi = Yi in steady state (but may be
different during transition)
 Simultaneous change in two (or
more) inputs is prohibited.
 The time between two changes must
be less than the time of stability.

5
Advantages and Disadvantages

• Advantages:
 Low power
 High performance
 No need for clock
• Disadvantages:
 Complexity of design process

6
Analysis : Example 1

y1
x Y1

y2
Y2

1. Find feedback loops and name feedback variables appropriately.


2. Find boolean expressions of Yi’s in terms of yi’s and inputs.

Y1 = x.y1 + x’.y2
Y2 = x.y1’ + x’.y2
7
Analysis
3. Draw a map:
 rows: yi’s
 columns: inputs
 entries: Yi’s
x x x
y1 y2 0 1 y1 y2 0 1 y1 y2 0 1

00 0 0 00 0 1 00 00 01

01 1 0 01 1 1 01 11 01

11 1 1 11 1 0 11 11 10

10 0 1 10 0 0 10 00 10

Y1 = x.y1 + x’.y2 Y2 = x.y1’ + x’.y2 (Transition Table) Y1 Y2


8
Analysis
4. To have a stable state, Y must be = y
(circled) 0
x
1y1 y2

00 00 01

01 11 01

(Transition Table) Y1 Y2
11 11 10

10 00 10

 At y1y2x = 000, if x: 0  1
 then Y1Y2: 00  01
 then y1y2 = 01 (2nd row): stable
9
Analysis
 In general, if an input takes the circuit to
an unstable state, yi’s change until a
stable state is found.
x
 General state of circuit: y1 y2 0 1

 y1y2x: 00 00 01

 There are 4 stable states: 01 11 01

 000, 011, 110, 101


11 11 10
 and 4 unstable states.
10 00 10

10
State Table
 As synchronous:
next state
present
state X 0 X 1

00 00 01
01 11 01
10 00 10
11 11 10

11
Flow Table
 As Transition Table (but with symbolic states):
x
0 1

a a b

b c b

c c d

d a d

12
Flow Table: Example 2
 Two states, two inputs, one output.
x1 x2
00 01 11 10

a a ,0 a ,0 a ,0 b ,0

b a ,0 a ,0 b ,1 b ,0

 Each row has more than one stable state.


 If x1 = 0, state is a.
 If x1x2 = 00  x1x2 = 10, then state becomes b.
 For x1x2 = 11, state is either a or b.
 If previously in x1x2 = 01, keeps state a,
 If previously in x1x2 = 10, keeps state b.
 Reminder: cannot go from 00 to 11. 13
Circuit Design
 From flow table to circuit:
 Assign a unique binary value to each state,
x1 x2 x1 x2
00 01 11 10 00 01 11 10
y
a a ,0 a ,0 a ,0 b ,0 0 0 ,0 0 ,0 0 ,0 1 ,0

b a ,0 a ,0 b ,1 b ,0 1 0 ,0 0 ,0 1 ,1 1 ,0

x1 x2 x1 x2
00 01 11 10 00 01 11 10
y y
0 0 0 0 1 0 0 0 0 0

1 0 0 1 1 1 0 0 1 0

Map for Y (=x1x2’+x1y) Map for output z (=x1x2y)


14
Logic Diagram

z = x1x2y
x1
x2 Y
Y = x1x2’+x1y

15
Race Condition
 If two (or more) state variables
change in response to a change in
an input, there is a race condition.
 E.g. from 00 to 11, due to delays
00  01  11 OR
00  10  11.

• Critical Race:
 If final steady state depends on the
order of changes in state variables.

16
Race: Examples
• Noncritical Cases:
x x
y1y2 0 1
y1y2 0 1

00 00 11 00 00 11

01 11 01 01

11 11 11 01

10 11 10 11

00  11 00  11  01
00  01  11 00  01
00  10  11 00  10  11  01

17
Race: Examples

• Critical Cases:
x x
y1y2 0 1
y1y2 0 1

00 00 11 00 00 11

01 11 01 01

11 11 11 11

10 10 10 10

00  11 00  11
00  01  11 00  01
00  10 00  10

18
Instability

x1 Y
x2 Y = (x1 y)’ x2
x1 x2
00 01 11 10
y
0 0 1 1 0
 For x1x2 = 11, there is no steady state.
  Oscillation.
1 0 1 0 0
 For x1x2 = 11, Y = y’  unstable.

19
Race Free State Assignment
 Must assign binary values to states such that:
 one change in an input may not cause two changes in state variables.
 because, due to delays, one of the variable change sooner and may stay in
an unwanted stable state.
 From a, if x1x2 = 10  11, must go to c and stay there.
 But by the following assignment, it may go to b and stay there.

x1 x2
00 01
00 01 11 10
a b
a a b c a

b a b b c

c a c c c c
 a and b must be different in one bit, 11
 a and c must be different in one bit.
20
Race Free State Assignment
 Impossible  add one more row.
x1 x2
00 01 11 10

a a b d a

b a b b c
00 01
c d c c c a b
d a - c -

 d is an intermediate c
(unstable) state.
d
10 11
 - means any value can be
assigned (Except d=10).
21
Example 2
x1 x2
00 01 11 10
00 01
a b a d a
a b
b b d b a

c c a b c

d c d d c d c
10 11

 If there were no diagonal transition, it would be


possible
 Impossible  add some more rows.

22
Example 2 y1 y2
x1 x2 00 01 11 10
00 01 11 10 y3
0 a b c g
a = 000 b a e a
1 e d f 0
b = 001 b d b a

c = 011 c g b c  b is adjacent to a, c, d
 c  a through g
g = 010 - a - -
 a  d through e
110 - - - -  d  c through f
00 01
f = 111 c - - c
a b
d = 101 f d d f

e = 100 - - d -

d c
23
10 11
Multiple-Row Method
In the multiple-row assignment, each state in the
original flow table is replaced by two or more
combinations of state variables.

Note that a2 is
adjacent to d2, c1,
b2.

24
MULTIPLE-ROW METHOD

 In multiple row assignment, each state in the original


flow table is replaced by two or more combinations of
state variables.
 There are 2 binary state variables for each stable state,
each being the logical complement of each other.
 For example, the original state a is replaced with 2
equivalent states a1=000 and a2=111.
 Note that a1 is adjacent to b1, c2 and d1 and a2 is
adjacent to c1, b2 and d2, and similarly each state is
adjacent to 3 states of different letter designation.

25
 The expanded table is formed by replacing each row of

the original table with 2 rows.


 For eg, row b is replaced by rows b1 and b2 and stable

state b is entered in columns 00 and 11 in both the


rows b1 and b2.
 After all the stable states have been entered, the
unstable states are filled in by reference to the
assignment specified in the map.
 When choosing the next state for a given present state,
a state that is adjacent to the present state is selected
from the map.
 In the original table, the next states of b are a and d for
the inputs 10 and 01, respectively.
 In the expanded table, the next states for b2 are a2 and
d1 because they are adjacent to b2. 26
Multiple-Row Method

The original
27
flow table
ONE HOT STATE ASSIGNMENT

 The one hot state assignment is an


another method for finding a race free state
assignment
 In this method, only one variable is active
or ‘hot’ for each row in the original flow
table, i.e. it requires one state variable
changes between internal state transitions.
 Consider a flow table.

28
Flow table:
State variables State Inputs X1 X2
F4 F3 F2 F1 00 01 11 10
0 0 0 1 A A B C C
0 0 1 0 B A B C D
0 1 0 0 C A B C C
1 0 0 0 D D B C D
4 state variables are used to represent the 4 rows in the
table.
 Each row is represented by a case where only one of the 4
state variables is a 1.
 A transition from state A to state B requires 2 state variable
changes; F1 from 1 to 0 and F2 from 0 to 1.
 By directing the transition from A to B through a new row E
which contains 1s where both states A and B have 1s.

29
 We require only one state variable change from
transition
A to E and then from transition E to B.
 This permits the race free transition between A and B.
 In general, we can say that, in row I of the table, state
variable Fi is 1 and all other state variables are 0.
 When a transition between row i and j is required, first
state variable Fj is set to 1 and Fi is set to 0.
 Thus each transition between 2 rows in the flow table
goes through one intermediate row.
 This permits the race free transition but requires 2 state
transitions.
 The following table is the complete one hot state
assignment flow table.

30
State variables State Inputs X1 X2
F4 F3 F2 F1 00 01 11 10
0 0 0 1 A A B C C
0 0 1 0 B A B C D
0 1 0 0 C A B C C
1 0 0 0 D D B C D
0 0 1 1 E A B - -
0 1 0 1 A - C C
0 1 1 0
F
G - B C -
1 0 1 0 H - B - D
1 1 0 0 I - - C -

When X1 X2=01 the transition from A to B is passing through the


dummy state E. Similarly, when X1X2=00 the transition from C
to A is passing through the dummy state F and so on.
31
Guidelines for State Assignment
• To try all equivalent state assignments, i.e.,
and exhaustive exploration of all possible
state assignments is a n-p complete problem.

There are guidelines that help


1. States which have the same next state for a given
input should be given adjacent assignments.
2. States which are the next states of the same state
should be given adjacent assignments
3. States which have the same output for a given
input should be given adjacent assignments.

32
Hazards
 Hazards definition.
 Hazards in combinational circuit.
 static hazard
 dynamic hazard
 Hazard free circuit.
 Hazards in sequential circuit
 Essential hazards

33
Hazards
Hazards are unwanted switching transients that
may appear at the output of a circuit because
different paths exhibit different propagation
delays.
Hazards occur in combinational circuits, where they
may cause a temporary false-output value.
When hazards occur in sequential circuits, it may
result in a transition to a wrong stable state.

34
Hazards in Combinational
Circuits
F1

F2

35
-> Assume that all the three inputs are initially equal to 1.
This causes the output of the gate 1 to be 1, that of gate 2 to be
0, and the output of the circuit to be equal to 1.

-> Now consider a change of x2 from 1 to 0. The output of gate 1


changes to 0 and that of gate 2 changes to 1, leaving the output
at 1.

-> However, the output may momentarily go to 0 if the


propagation delay through the inverter is taken into
consideration.

-> The delay in the inverter may cause the output of gate 1 to
change to 0 before the output of gate 2 changes to 1.

36
-> In that case, both inputs of gate 3 are momentarily equal to 0,
causing the output to go to 0 for short interval of time that the
input signal from x2 is delayed while it is propagating through
the inverter circuit.

-> If the circuit is implemented in SOP,


Y=x1 x2+x2’ x3
This type of implementation may cause the output to go to 0
when it should remain at 1. This type is called as static 1-hazard.

-> If the circuit is Implemented in POS,


Y=(x1+x2’) (x2+x3)
Then the output may momentarily go to 1 when it should remain
0. This type is called as static 0- hazard.

-> A third type of hazard, known as dynamic hazard, causes the


output to change three or more times when it should change
from 1 to 0 or from 0 to 1.
37
Hazards in Combinational
Circuits

38
Hazards in Combinational
Circuits

The hazard exists


because the change of
input results in a
different product term
covering the two
minterms.

39
 In the above K-map, the change in x2 from 1 to
0 moves the circuit from minterm 111 to minterm
101. The hazard exists because the change of input
results in a different product term covering the two
min terms.
 Min term 111 is covered by the product term
implemented in gate 2.
 whenever the circuit must move from one
product term to another, there is a possibility of a
momentary interval when neither term is equal to 1,
giving rise to an undesirable 0 output.

40
Eliminating hazards

 The remedy for eliminating hazard is to


enclose the two minterms in question with
another product term the overlap both the
groupings.

 This is shown in the following K-map,


where two min terms that cause the hazard
are combined into one product term.

41
Hazards in Combinational
Circuits

The remedy for eliminating


a hazard is to enclose the
two minterms in question
with another product term
that overlap both grouping.

42
HAZARD FREE CIRCUIT

The following circuit is the hazard free circuit.


The extra gate in the circuit generates the product
term x1 x3.

In general hazards in combinational circuits can


be eliminated covering any two minterms that
may produce a hazard with a product term
common to both.

The removal of hazard requires the addition of


redundant gates to the circuit.

43
Hazards in Combinational
Circuits

44
HAZARDS IN SEQUENTIAL
CIRCUITS

45
ESSENTIAL HAZARDS
 There is another type of hazard that may occur in
asynchronous sequential circuits, called essential
hazard.
 An essential hazard is caused by unequal delays
along two or more paths that originate from the same
input. An excessive delay through an inverter circuit in
comparison to the delay associated with the feedback
path may cause such a hazard.
 Essential hazards cannot be corrected by adding
redundant gated as in static hazards.
 The problem that they impose can be corrected by
adjusting the amount of delay in the affected path.

46
 To avoid essential hazards, each feedback
loop must be handled with individual care to
ensure that the delay in feedback path is long
enough compared to delays of other signals
that originate from the input terminals.

 This problem tends to be specialized, as it


depends on the particular circuit used and the
amount of delays that atr encountered in its
various paths.

47
Essential hazards
• A critical race between an input signal change and
a feedback signal change – may cause an incorrect
state transition

• Incorrect behaviour depends upon specific delays


in gates/interconnections

• “If from any stable state, the final state reached


after one change in an input is different to that
reached after three changes in that input, then an
essential hazard exists”

48
Essential hazards

Starting from PRY1Y2 = 1010


The final state can be 00 or 01
for one or three changes in P
But, depending upon circuit
delays, a single change in P
may cause an incorrect
transition to state 01

• What circuit delays?


We must ensure that input signal delays are smaller than
feedback signal delays.

49
Essential hazards

Buffer delay
increased here

50
ELIMINATING ESSENTIAL HAZARDS

 We can avoid essential hazards in asynchronous circuits


by implementing them using SR latches.
 A momentary 0 signal applied to the S or R inputs of a NOR
latch will have no effect on the state of the circuit.
 Similarly, a momentary 1 signal is applied to the S and R
inputs of a NAND latch will have no effect on the state of the
latch.
 Let us consider a NAND SR latch with the following
Boolean function:

S= AB+CD
R= A’C

51
A
B
Q
C
D

A’
Q’
C
The first level consists of NAND gates that implement
each product term in the original Boolean expression
of S and R. The second level forms the cross coupled
connection of the SR latch with the inputs that come
from the outputs of each NAND gate in the first level.
52

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