Module 2 VLSI DESIGN

IDEAL INVERTER VOLTAGE TRANSFER CHARTERISTIC

Boolean (or logic) value of "1" can be represented by a high

voltage of VDD
Boolean (or logic) value of "0" can be represented by a low
voltage of 0.
ACTUAL INVERTER VOLTAGE TRANSFER CHARTERISTIC

VOH -> max output voltage when

output is “1” VOL -> min output voltage
when output is “0”
VIL -> max input voltage which can be
interpreted as “0” VIH -> min input voltage
 NOISE IMMUNITY AND NOISE
MARGINS
• The ability of an inverter to interpret an input signal within a voltage
range as either
a logic “0" or as a logic "1" allows digital circuits to operate with a certain
tolerance.
• These noise tolerances for digital circuits is called noise margins
(NM).

Assume 3 inverter are connected in series

 CMOS Inverter- Operation

VSBp  VSBn  0

Linear
region
pMOS

Saturation
region pMOS
VOH calculation
when Vin < VT0n, the nMOS transistor is cut-off. At the
same time, the pMOS transistor is on, operating in the
linear region. Since the drain currents of both transistors
are approximately equal to zero

=0

Vout  VOH  VDD

VOL calculation
when the input voltage exceeds (VDD + VT0p ), the pMOS
transistor is turned off. In this case, the nMOS transistor
is operating in the linear region,
 0
=

Vout  VOL 
VIL calculation 0

• when Vin > VT0n (in Region B), the nMOS transistor starts conducting in
saturation
mode and the output voltage begins to decrease.
• The slope of the VTC is equal to (-1), i.e., (dV0ut/ dVin )= -1, when the input voltage is
Vin = VIL. Note that in this case, the nMOS transistor operates in saturation while the
pMOS transistor operates in the linear region.

Substitut
e
 -------
(1)
Differentiate on both side Vout
w.r.t. Vin
k 'n  W  2V  V  k p  W   2 V  V 

dVin  2Vout  VDD  dVin 
'
  VDDV T0p dV
out out
 in T0n  
out DD in
2  L n 2  L  p2 V
 dV

Substitute Vin = VIL dVou t  1
dVin
and
W '  W

k   VIL  VT0n   p   V  V
'
n
DD  VIL  VDD  VT0p
 V V 
 L n k  L  p out out
DD


kR VIL  VT0n   2Vout  VDD  VIL 
 k V V   VDD T0pV Rk 
2V
R IL IL out
V

T0n
2Vout  VDD  VT0p  kRV
VI T0n
L  1
k
R

VIH calculation

When the input voltage is equal to VIH, the nMOS transistor operates in the
linear region, and the pMOS transistor operates in saturation

Substitut
e
-------
(2)
 Differentiate on both side Vout
w.r.t. Vin
k 'n  W  2 V  V out  dVout  k ' 2V V V
 in T0n
 dV 2Vout  2Vout   p  W   in DD

T0p
2  L n  dVin dV in  2  L p
 dV
Substitute in = V and dV  1
ou t in
V IH
W W
k 'n    VIH  VT0n  2Vout  '
p   V  V
IH DD  VT0p
 L n k  L p


 2V   V  V V 
k R  VIH  VT0n
out DD
T0p
IH

- VIH (1 k R )  k R (VT0n  2Vout ) 

V T0p
VDD
VIH (1 k R )  VDD
VT0p  k R (VT0n 
2Vout )
 VIH  VDD  VT0p  k R (VT0n  2Vout )
(1 k ) R

Vth calculation

Vin  Vout  Vth

Substitut
e

k R Vin  V T0n 2  Vin

V  VT0p 
take square root on both
DD
2

side
 k V V    V V
T0p
V 
1
R in T0n in DD

 kR V in  VDD  k R VT0n

VVthT0p VDD  VT0p  k R VT0n

1 k R
Design of CMOS 
Inverter
kR
V  V  V
DD T0p th

  V  V th T0n

 2
kR  VDD  VT0p  V th 

 Vth  VT0n
 
2
k R   0.5VDD  T0p 
  0.5VDD  VT0n 
V
kR 
1
For a symmetric inverter with VT0n = | VT0p | and kR = 1, the VIL

VIL

voltage can be
2Vout  VDD  VT 0p  kR VT

2Vout  VDD
0n
  1 kR 2
Substitute this Vin = VIL in eq. (1) and
determine VIL
1
VIL 
8
3VDD  2VT0n

Similarly determine VIH using
eq. (2)
1
VIH 
8
5VDD  2VT0n

Note that the sum of VIL and VIH is always equal to VDD in a symmetric
inverter.

VIL  VIH  VDD

Ex. If kn’ =140μA/V2 kp’ =60μA/V2 Vtn = 0.7, Vtp = -0.7 and
VDD =3V Find (a) transistor size ratio so that Vth = 1.5
V
(b) Vth if transistor are same size
2
 V  V DD  V 
T 0p t h  3 - 0.7 1.5 
2

a R  
.  Vth  VT 0n   1.5  1
0.7
140(W/L) W W
1  60(W/L) n  p  2.33
p L  L n


b
140
. k R  60 
2.33
 VT 0p 
Vth  VDD k R VT 0n 3  0.7  2.33 
1 k R

0.7
 1
3.368
 2.526 
1.33
 
2.33
 Calculate the noise margins of the
circuit

it is not a symmetric inverter

k R  2.5, VOL  0V and VOH 

5V 2V  V  V  k V
2Vout  3.3  0.7 VIL  0.57Vout 
VIL


 out 1DD
kR T 0p R
VIL
1.5 0.71
T 0n
3.5this Vin = VIL in eq. (1) and
Substitute
determine Vout

2.5(0.57V  0.71 0.6) 2  2(0.57V  0.71 3.3  0.7)(V  3.3)  (V  3.3) 2

out out out
out
 2
0.66Vout  0.05Vout  6.65 
0
Vout  3.14V

VIL  0.57Vout  VIL  0.57 3.14  0.71 

0.71 1.08V

Calculate VIHV  k (V  2V )
VIH  VDD
T 0p R T 0n out
VIH  3.3 - 0.7  2.5(0.6  VIH  1.17 out

(1 kR ) 2Vout ) 3.5 1.43V

Substitute this Vin = VIH in eq. (2) and

determine Vout


2.5 2(1.17 1.43V
out  0.6)V out  V out
2
(1.43Vout 1.43)2

 2.61 out
2
 out  2.04  Vout 
0.27V
VIH  1.17 VIH  1.17 1.43 0.27 
1.43Vout 1.56V

NM L  VIL  VOL 
1.08V NM H  VOH  VIH
 1.75V
 MOS INVERTERS:
Switching Characteristics and Interconnect effects

• The switching characteristics of digital integrated circuits and, in particular, of inverter circuits, essentially
determine the overall operating speed of digital systems.
• The capacitances Cgd and Cgs are primarily due to gate overlap with diffusion, while Cdb and Csb are
voltage-dependent junction capacitances.
• The capacitance component Cg is due to the thin-oxide capacitance over the gate area.
• The lumped interconnect capacitance Cint. which represents the parasitic capacitance contribution of the metal
or polysilicon connection between the two inverters.
• Assume that a pulse waveform is applied to the input of the first-stage inverter to analyze the time-domain
behavior.
 MOS INVERTERS:
Switching Characteristics and Interconnect effects

• The problem of analyzing the output voltage waveform is fairly complicated, even for this relatively simple circuit,
because a number of nonlinear, voltage-dependent capacitances are involved.
• To simplify the problem, we first combine the capacitances & will be called the load capacitance, Cload

• Cload = Cgdn + Cgdp + Cdbn + Cdbp + Cint + Cg -------------(6.1)

• In particular, Csbn and Csbp have no effect on the transient behavior of the circuit since the source-to-substrate voltages
of both transistors are always equal to zero.
• The capacitances Cgsn and Cgsp are also not included in (6.1) because they are connected between the input node and
the ground (or the power supply).
• The capacitance terms Cdbn and Cdbp in (6.1) are the equivalent junction capacitances calculated for a particular output
voltage transition.
• By definition, pLH is the time delay between the V50%-transition of the rising input voltage and the V50 -transition of
the falling output voltage.
• Similarly,pLH is defined as the time delay between the V50 -transition of the falling input voltage and the V50%-
transition of the rising output voltage.
 Calculation of Delay Times: Average Current Method

• The simplest approach for calculating the propagation delay times pHL and pLH is based on estimating the
average capacitance current during charge down and charge up.
• If the capacitance current during an output transition is approximated by a constant average current Iavg the delay
times are found as,
 Calculation of Delay Times

• The average current during high-to-low transition can be calculated by using the current values at the beginning and the
end of the transition.

• The average capacitance current during low-to-high transition is

Calculation of Delay Times: Drawbacks of Average Current Method

• The average-current method is relatively simple and requires minimal calculation, it neglects the
variations of the capacitance current between the beginning and end points of the transition.
• Do not provide a very accurate estimate of the delay times.
• This approach provides rough, first-order estimates of the charge-up and charge-down delay times.
Calculation of Delay Times: Solving the state equation of the
output node in the time domain.

• The propagation delay times can be found more accurately by solving the state
equation of the output node in the time domain.
• Note that the capacitance current is also a function of the output voltage.
 t0 < t t1’ < t <
<t1’ : t1 :
d Vout tt 1
i D n  Cload dt Vout V50%
 dt 
  1 
t t1
i D n dVout
Cload C Vout VOH VT 0 n 
dt   i d Vout ' load
V V
Dn tt 1
2C
out 50%
 1 d

dt   k nload V V V
Vout

' 2
tt 1
t t1
 2(VOH - VT0n )Vout - Vout
Vout VOH VT 0 n
 1  

out OH T0
' n
dVout
 dt 
t t0 Vout OH
 iDn 
=V
C load 2C load 1  Vout V50%
tt1 ' Vout VOH V T 0
'
t1  t 1   ln Vout 
C n k n 2(VOH - VT0n )  2(VOH - VT0n ) - out  Vout VOH V T 0
 dt  k
t 0 n (V load
V
)T 0n
2 Vout  OH
V n

t OH V
2
d Vout ' 1  2(VOH - VT0n ) -V50% 
t1  t1  Cload ln 
t't  2CloadVT k n (VOH - VT0n  V50% 
 k n (V 0n
OH V T 0n ) 2 )
1 0
AN
D
  PHL  n n  Rn  Cload
0.693
 PLH  0.693 p p  R p  Cload

rise time and fall time

f

 2.2 n
 Power Dissipation
Since the CMOS inverter does not draw any significant current from the power source in both of its
steady-state operating points (Vout = VOH and Vout = VOL), the DC power dissipation of this circuit is almost
negligible.

PDC  I DD  VDD

IDD is the DC current from power supply (Ideally IDD = 0)

leakage currents cause IDD > 0, define quiescent leakage
current, IDDQ (due largely to leakage at substrate junctions)
Pdyn, power required to switch the state of a gate
– charge transferred during transition, Qe = Cload x VDD
– assume each gate must transfer this charge per clock cycle
– P_average = VDD Qe f
= Cload xVDD2 x f,
Power increases with Cload and frequency, and strongly with VDD (second
order).
Total Power  IDDQ VDD  CV
load DD 2 f
CMOS Logic Circuits

CMOS NOR2 (Two-Input NOR) Gate

Output  A 
B
• Assuming that both input voltages switch simultaneously, i.e., VA = VB .
• Assumed that the device sizes in each block are identical,
• and the substrate-bias effect for the pMOS transistors is neglected for simplicity.

Two nMOS – saturation

M3 – linear
M4 - saturation
 Kn
VDD  VTp  2 VTn
p
Vth (NOR2)
 K
 K 
1 2 n 
K 
 p


If Kn =
Kp
in order to achieve a switching threshold voltage of VDD/2 for
simultaneous switching, we have to set VTn = IVTpI and Kp = 4Kn .By
increasing Wp

The multiple-input NOR gate can also be reduced to an equivalent inverter,

 CMOS NAND (Two-Input NAND)
Gate

• Assuming that both input voltages switch simultaneously, i.e., VA =

VB .
• Assumed that the device sizes in each block are identical,
• and the substrate-bias effect for the pMOS transistors is neglected for
simplicity.
  1 K n
VTn
VDD  VTp 2
p
Vth (NAND2)
  1 K 
K n
1 
 2 Kp 

If Kn = and VTn = IVTpI, the switching threshold of the NAND2 gate is not equal
Kp to VDD/2
in order to achieve a switching threshold voltage of VDD/2 for
simultaneous switching,
we have to set VTn = IVTpI and Kn = 4Kp .By increasing Wn, but μn > μp so
we can keep Wn =Wp
Design of complex logic
circuits
Out  AB 
C
Z  ( A  B).(C 
Out  A(D  E) 
D)
BC
XOR XNOR
Gate Gate

Vout  AB  AB Vout  AB 
AB
 AA  AB  AB 
BB
 A( A  B)  B( A 
12
B)
Transistor
 (A 
 (A  B)( A
B)( A  B) required
B)
 (A  B)  ( A  B)
 AB  AB

12 Transistor
required
Full adder Circuit (one bit
adder)
sum_out  ABC  (A  B  C)carry_out
28 Transistor required
Layout of 2 input NOR
Gate VDD

B
A
Stick OUT
Diagram
VD
D

B
A OUT
GND

GN
Layout of 2 input NAND
VDD
Gate

A B

Stick OUT
Diagram
VD
D

A B
OUT
GND

GN
 VD
D
Out  AB 
C

A B C

OUT

GN
Out  A(D  E)  Euler-path: find a common Euler path for both nMOS and pMOS
netwrorks. The Euler path is defined as an uninterrupted path that traverses
BC each edge (branch) of the graph exactly once.

pMOS N/W nMOS N/W

Common Eular Path = E-D-A-B-C

 Stick
Diagram Draw Layout
VD Diagram ?
D

E D A B C OUT

GN
D
The equivalent-driver (W/L) ratio of the pull-down network
consisting of five nMOS transistors is,
1. The simplified layout of a CMOS complex logic circuit is given below. Draw the corresponding circuit
diagram, and find an equivalent CMOS inverter circuit for simultaneous switching of all inputs, assuming
that (W/L)p = 15 for all pMOS transistors and (W/L) = 10 for all nMOS transistors