UNIT V: CMOS TESTING

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VLSI Design
 Outline
 Introduction
 Testing
 Logic Verification
 Silicon Debug

 Manufacturing Test

 Fault Models
 Observability and Controllability
 Design for Test
 Scan
 BIST

 Boundary Scan

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 Definition of Testing
 A known input stimulus is applied to
a unit in a known state, and a known
response can be evaluated.

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 VLSI Realization Process
Customer’s need

Determine requirements

Write specifications

Design synthesis and Verification

Test development
Fabricatio
n
Manufacturing test

Chips to customer
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 Chip photo
SoC Flash Memory

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24/12/03 System Arch 2008 (Fire Tom Wada)
 FAULTS
If anything can go
wrong, it will.

Murphy’s Law
 Testing
 Testing is one of the most expensive parts of
chips
 Logic verification accounts for > 50% of design
effort for many chips
 Debug time after fabrication has enormous

opportunity cost
 Shipping defective parts can sink a company

 Example: Intel FDIV bug

 Logic error not caught until > 1M units shipped
 Recall cost $450M (!!!)

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 Logic Verification
 Does the chip simulate correctly?
 Usually done at HDL level
 Verification engineers write test bench for

HDL
 Can’t test all cases
 Ex: 32-bit adder
 Test all combinations of corner cases as
inputs:
 0, 1, 2, 231-1, -1, -231, a few random numbers
 Good tests require ingenuity
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 Silicon Debug
 Test the first chips back from fabrication
 If you are lucky, they work the first time
 If not…
 Logic bugs vs. electrical failures
 Most chip failures are logic bugs from inadequate
simulation
 Some are electrical failures
 Crosstalk
 Dynamic nodes: leakage, charge sharing
 Ratio failures
 A few are tool or methodology failures (e.g. DRC)
 Fix the bugs and fabricate a corrected chip

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 Think about testing from the
beginning
 Simulate as you go
 Plan for test after fabrication

 “If you don’t test it, it won’t

work! (Guaranteed)”

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 Defects
 Defects: physical problems that occur in
silicon
 Common Silicon CMOS defects:
 Gate-oxide shorts

 Insufficient doping

 Process or mask errors

 Open and plugged vias

 Short to power (Vdd) or Ground (Vss)

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 Defects

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 • Teradyne A575 Tester

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 LTX FUSION HF ATE

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 Verification vs. Test
Verification Test
• Verifies correctness of • Verifies correctness of
design. manufactured hardware.
• Performed by • Two-part process:
simulation, formal – 1. Test generation: software
methods. process executed once during
• Performed once prior to design
manufacturing. – 2. Test application: electrical
tests applied to hardware
• Responsible for quality
• Test application performed on
of design.
every manufactured device.
• Responsible for quality of devices.
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 Testing Procedure:
• Apply input vectors one at a time
• Examine each resulting output vector
– Compare value to "known good" value
– If different, chip is faulty
• Native approach to testing:
– Use all possible input vectors (2n for n inputs)
– Impractical for all but very small circuits
• Alternative approach:
– Model things that can go wrong in design as faults
– Find test vectors that expose faults
– Find shortest set of vectors that expose all faults
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 Why Test at the Chip
Level?
Rule of Thumb: A test escape at
one level of packaging costs ten
times more to detect at the next
higher level of packaging.

Moral: Detect failure at the lowest

package level.

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 Main Difficulties in Testing
• Miniaturization Physical access
difficult or impossible.
• Increasing complexity Large
amount of test data.
• Number of access ports remains
constant Long test application
time.
• Testing accounts up to 50% of
product development efforts.

• The key to successful testing lies in

the design process.

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 Main Difficulties in Testing (Cont..)
• VLSI circuits are difficult to test due to their
inherent complexity and pin limitations

• Testability can be enhanced by DFT (Design

For Testability) methods like scan design
and BIST (Built In Self Test).

• Current logic BIST methods lack generality

and often have high overhead

• New and better methods are needed!

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 Testing Challenges (1)
• Increasing Level of Integration
– Testing requires control and observation of
signals in the circuit from its pins

Solution: Use DFT to increase controllability and/or

observability of signals in the test mode.

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 Testing Challenges (2)

Rising Cost of ATE (Automatic Test Equipment)

• Automatic test equipment or Automated test equipment
(ATE) is any apparatus that performs tests on a device,
known as the device under test (DUT), equipment
under test (EUT) or unit under test (UUT), using
automation to quickly perform measurements and
evaluate the test results.

–Without cost-cutting measures the cost of testing could

easily exceed the cost of manufacturing.

Primary Solution: BIST (but also higher levels of fault

modeling and greater use of functional tests)

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 Testing Challenges (3)
• Inadequate Fault Modeling
– A new technology (e.g. when going from 90
nm to 65 nm feature size) can introduce
new types of likely defects that are not
modeled by the existing fault models

Solution: No easy general solution.

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 Testing Goals
• High coverage of real defects
• Short testing time
• Easy test generation
• Fault diagnosis
• Design for testability (DFT) makes it easier
to produce high-quality tests
• Built-in self-test (BIST)

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 Tools for Testing
• Automatic Test Pattern Generation (ATPG)
– Searches for a test for every possible fault
– Attempts to minimize total number of vectors
• Fault Simulator
– Simulates response of faulty circuit to a set of test
vectors
– Measures fault coverage for a given set of test vectors
• Design-for-Testability, Built-In Self Test
– Ways to make testing easier, especially for sequential
circuits
– More about these later
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 Fault Coverage
• Used as measure of test quality
Detected Faults
Fault Coverage 
Number of Faults

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 Testing Categories
• Functionality tests
– Done at each level of hierarchy (software+model)
Higher levels of abstraction  faster
– Use diagnostic reasoning to find the bug
• Manufacturing tests
– Performed on the final product (wafer or package)
– Transistor-level simulation and testing
– “Are there any disconnected wires?”
“Any layer-to-layer shorts?”
“Is the product tolerant to Vdd variations?”

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 Manufacturing Test
• A speck of dust on a wafer is sufficient to kill chip
• Yield of any chip is < 100%
– Must test chips after manufacturing before delivery to
customers to only ship good parts
• Manufacturing testers are
very expensive
– Minimize time on tester
– Careful selection of
test vectors

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 The Chip Testing Process

Test
Responses R Comparator Pass: R=R’
Fail: otherwise
Unit R’
Under Expected
Responses
Test Test
Patterns T
(UUT) Tests

ATE

ATE: Automatic Test Equipment

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 Test Generation and Fault-
Coverage Analysis
•Obtain a sequence of test patterns with desirable fault coverage.
• Determine the expected response of the UUT to the test sequence.

Test
Responses R Comparator Pass: R=R’
Fail: otherwise
R’
Expected
UUT Responses
Test
Patterns T
Tests

ATE

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 Design for Testability (DFT)

Design/modify the circuit so that it is easier to test.

Test
Responses R Comparator Pass: R=R’
Fail: otherwise
R’
Expected
UUT Responses
Test
DFT Patterns T
Overhead Tests

ATE

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 Self Testing
 Built-in self test (BIST)
 Chip itself generates test vectors (internally)
 Dedicated sub-circuit to generate pseudo-random
test vectors
 Use “linear feedback shift register (LFSR)” to

generate test vectors

 Use signature to check the integrity
 Apply sequences of input vectors and combine

the output into a signature

 Shift in initial seed and shift out the signature

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 DFT Approaches
Ad Hoc Design Rules
• Control/test point insertion
• Circuit restructuring, e.g. feedback control
• Special timing considerations

Systematic Design Methods

• Compact testing (signature analysis)
• Scan design

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Fault Models
Faults

 Stuck-at-0 (SA0), stuck-at-1 (SA1)

 Node tied to Vdd or GND
 Bridging (shorting)
 Two wires tied together on one or more layers
 Stuck-open
 Break in a wire disconnects two wires
 Delay faults
 Parameter variations slow down a gate
 Path-delay faults
 Cumulative delay faults along a path
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Stuck-At Faults
 How does a chip fail?
 Usually failures are shorts between two
conductors or opens in a conductor
 This can cause very complicated behavior
 A simpler model: Stuck-At
 Assume all failures cause nodes to be
“stuck-at” 0 or 1, i.e. shorted to GND or V DD
 Not quite true, but works well in practice

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 Fault Models - Stuck-at-0/1
• Assume that every fault forces a gate output to be
– Always zero - stuck-at-0
– Always one - stuck-at-1
• Testing procedure: for each node in a design
– Assume that node is S-A-0
– Find a test that reveals this fault
– Assume this node is S-A-1
– Find a test that reveals this fault
– For each circuit node
• One test vector may detect more than one fault!
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 Stuck-At Faults in Gates

a b OK SA0 SA1 a b OK SA0 SA1

0 0 1 0 1 0 0 1 0 1
0 1 1 0 1 0 1 0 0 1
1 0 1 0 1 1 0 0 0 1
1 1 0 0 1
1 1 0 0 1

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NAND NOR
 Testing Simple Gates for Stuck-At Faults

• Assume gate output is S-A-0

– Apply a test vector that should generate a 1
– If output is 0, then gate is faulty!
• Assume gate output is S-A-1
– Apply a test vector that should generate a 0 output
– If output is 1, then gate is faulty!

NAND Gate: NOR Gate:

Test for S-A-0 with inputs: Test for S-A-0 with inputs:
00, 01, or 10 00
Test for S-A-1 with inputs: Test for S-A-1 with inputs:
11 01, 10, or 11
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 More about Stuck-At Fault
Models
• Drawback: not all real faults have this behavior!
– Open circuit - may float between values
– Short circuit - may change as shorted output changes
• Drawback: we may more than a single fault
• Even so, stuck-at fault models are used extensively
– Easier to work with than other models
– Shown to give good results even for non-stuck-at
faults
• Alternative: stuck-open model (see book)

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 Fault Models
 Stuck-at covers most of the faults
 Shown: short (,), open ()

Z , : x1 sa1
x1
 : x1 sa0 or
 x3 x2 sa0
x2 

12/03/24 [©Prentice Hall]

Fault Models
 Stuck-at – open does not cover all faults
 Example: Sequential effect:
x1 x2 Z
x1 x2
Z 0 x 1
x1 1 1 0
1 0 Zn-1
x2

 Needs two vectors to detect (1,1) (1,0)

 Other options:
 Use stuck-open or stuck-short models
 Problem: too expensive! [©Prentice Hall]
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Generating and Validating Test Vectors

 Automatic test-pattern generation (ATPG)

 For given fault, determine test (aka excitation) vector that
will propagate error to observable output
 Most available tools: combinational networks only

 Fault simulation
 Determine minimal test vectors that will sensitize circuit to

the fault
 Simulates correct network in parallel with faulty networks

 Structure of logic may make some faults untestable

 Both require adequate models of faults in CMOS integrated

circuits

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PRSG (Pseudo-Random Sequence
Generator)
 Linear Feedback Shift Register

 Shift register with input taken from XOR of state

Step Q
0 111
1
CLK
2
Q[0] Q[1] Q[2]
F lo p

F lo p

F lo p

D D D 3
4
5
6
7
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PRSG
 Linear Feedback Shift Register
 Shift register with input taken from XOR of state

Step Q
CLK
0 111
Q[0] Q[1] Q[2]
1 110
F lo p

F lo p

F lo p
D D D
2
3
4
5
6
7
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PRSG
 Linear Feedback Shift Register
 Shift register with input taken from XOR of state

Step Q
CLK
0 111
Q[0] Q[1] Q[2]
1 110
F lo p

F lo p

F lo p
D D D
2 101
3
4
5
6
7
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PRSG
 Linear Feedback Shift Register
 Shift register with input taken from XOR of state

Step Q
CLK
0 111
Q[0] Q[1] Q[2]
1 110
F lo p

F lo p

F lo p
D D D
2 101
3 010
4
5
6
7
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 PRSG
 Linear Feedback Shift Register
 Shift register with input taken from XOR of state

CLK Step Q
Q[0] Q[1] Q[2] 0 111
F lo p

F lo p

F lo p
D D D
1 110
2 101
3 010
4 100
5
6
7
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PRSG
 Linear Feedback Shift Register
 Shift register with input taken from XOR of state

Step Q
CLK
0 111
Q[0] Q[1] Q[2]
1 110
F lo p

F lo p

F lo p
D D D
2 101
3 010
4 100
5 001
6
7
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PRSG
 Linear Feedback Shift Register
 Shift register with input taken from XOR of state
 Pseudo-Random Sequence Generator

Step Q
CLK 0 111
Q[0] Q[1] Q[2] 1 110
D D D
F lo p

F lo p

F lo p
2 101
3 010
4 100
5 001
6 011
7
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 PRSG
 Linear Feedback Shift Register
 Shift register with input taken from XOR of state

Step Q
CLK 0 111
Q[0] Q[1] Q[2] 1 110
F lo p

F lo p

F lo p
D D D
2 101
3 010
4 100
5 001
6 011
7 111
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(repeats)
Test Vector Generation: Path
Sensitization
 Work forward and backward from node of interest to determine
values of inputs to test for fault

 At the site of the fault, assign a logical value complementary to the

fault

 Select a path from the circuit inputs through the site of the fault to
an output, the path is sensitized if the inputs to the gates along the
path are set so as to propagate the value at the fault site

 Determine the primary inputs that will produce the required values
at the gate inputs as determined above

[©Hauck]
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Automatic Test Pattern
Generation
 Eases generation of
test vectors.
 Reduces cost of test
 More efficient test
vectors
 Reduction in cycle time
 Provides a
deterministic quality
metric.

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 ATPG

no error error
0
 0/1
0 1/0 1/0
1 1
1

 Could we check for a stuck at one error at a (s-a-1(a)) ?

 Solution (just guessing):
 f='1' if there is an error

  a='0', b='0' in order to have f='0' if there is no error

 g='1' in order to propagate error

 c='1' in order to have g='1' (or set d='1')

 e='1' in order to propagate error

 i='1' if there is no error & i='0' if there is error

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 Path Sensitization Example
 Trigger the fault
 Make it propagate to output

sa0
1
Fault enabling 1 1
1 Out
1
Fault propagation 1 0
0

[©Prentice Hall]
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Level Sensitive Scan Design
(LSSD)
 Known as scan-based test
 Scan path (shift register) links all state elements in circuit
 Observe and control all states
 Requires 3 extra pins and a bit more logic in FFs
 All tests become combinational
 Very slow — shift in test vector and shift out output
vector serially — partial scan
paths only use necessary amount
 Easy to extend to system level

[©Hauck]
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Using Scan Design

 Shift in to set FF values

 Shift out to read FF values
 Scan variations
 Full scan - require scan in all flip-flops
 Partial scan - require scan in some flip-flops
 Boundary scan - use scan for block I/Os (often
used in board-level test)

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 Scan Flip-Flop

Scan-out
Scan-out Din 0
Din
Dout D Q Dout
Scan-in Scan-in 1
Q Q
Test
Test
Clock Q
Clock

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Scan design

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 Scan Based Test
ScanIn ScanOut

Out

Register
Register

In Combinational Combinational
Logic Logic
A B

Test

1
2

N cycles scan in 1 cycle N cycles scan out

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 Scan-Based Test Operation

In0 In1 In2 In3

test test test test

test test test test

Scan In
Scan
Out
Latch Latch Latch Latch

Out0 Out1 Out2 Out3

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 Limitations of a single serial scan
chain
For chips with a large number of flop-flops, serial
shifts can take a quite long time.
Hence, it becomes necessary to provide several
scan chains.
 Trying to avoid serial shifts by generating test
patterns internally and by also storing the
results internally.
 Compaction of circuit response in a signature.
Shifting the entire result out becomes obsolete,
we just shift out the signature.
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 Signature analysis

Response of circuit to sequence of test patterns compacted in

a signature. Only this signature is compared to the golden
reference.
Exploit an n-bit signature register as well as possible:

 try to use all values possible for that registers!

In practice, we use shift-registers with linear feedback:
Response
of circuit to
sequence XOR n-bit shift register
of test
vectors Signature
 Using proper feedback bits, all values possible for
the register can be generated.
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 Built-in Self-Test (BIST)
Include test-vector generation and response-analysis circuitry within the chip.

Test
Responses R Comparator Pass: R=R’
Fail: otherwise
Unit R’
Expected
Under Responses
Test
Test Patterns T
Tests

BIST Logic
Chip Boundary
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70
 Built-In Self-Test (BIST)
 Self-test logic, consisting of pattern generator, response analyzer & test manager, is built into the chip.

 The test manager executes the self-test and accumulates its result for transmission to an an external pin or higher
package-level test manager.

System
Board Chip

Test
Manager
Test
Manager
Test
Manager Pattern Response
CUT
Generator Analyzer

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71
Built-In Self Test (BIST)
 Goal: provide limited testing within the chip
itself
 Typical approach: use Linear Feedback Shift
Register (LFSR)
 Structure: shift register with exclusive-OR

feedback
 "Pseudo-random" state sequence

D Q D Q D Q D Q

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BIST (cont'd)
 Applications of LFSRs
 Generate pseudo-random test vectors
for self-test
 Use as signature analyzer to
compress output vectors
TEST INPUT

D Q D Q D Q D Q

CLK

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 BIST (cont'd)
 Applications of LFSRs
 Generate pseudo-random test vectors for self-

test
 Use as signature analyzer to compress output
LFSR
vectors

Circuit Under Test

Signature Analyzer

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 BIST: Signature Analysis
 Compress the output vector
 Time compression (count # of transitions)

 OR: compute output parity vector

 Example: time compression:

In
Counter

[©Prentice Hall]
12/03/24
 BIST Hardware Structures
 Response
 Pattern Generators: Compressor:
 LFSR  XOR Trees
 Binary Counter -Level Counter
 XOR Trees  Transition Counter

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 Replacing serially shifted test pattern
by pseudo random test patterns
Shifting in test patterns can be avoided if we generate
(more or less) all possible test patterns internally with a
pseudo-random test pattern generator.

Pseudo- DUT Signature Compare

random analysis with
test pattern register reference
generator

Effect of pseudo random numbers on coverage to be

analyzed.
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Signature analysis register shifted-out at the end of
Boundary Scan Interface

Boundary scan is accessed through five pins

TCK: test clock

TMS: test mode select

TDI: test data in

TDO: test data out

TRST*: test reset (optional)

 Chips with internal scan chains can access the

chains through boundary scan for unified test
strategy.
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 Boundary Scan (JTAG)
Printed-circuit board
Logic Packaged IC

connections
Scan-in

Normal
si so
Scan-out
scan path

Bonding Pad
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[©Prentice Hall]
 JTAG (Boundary scan)

JTAG defines a 4..5-wire serial

interface to access complex ICs ..
Any compatible IC contains shift
registers & FSM to execute the
JTAG functions.
TDI: test data in; stored in

instruction register or in one of

the data registers.
TDO: test data out
TCK: clock
TMS: controls the state of the
test access port (TAP).
Optional TRST* is reset signal.

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 JTAG (Boundary scan) (2)
 Defines method for setting up a scan chain on a PCB

Source: http://www.jtag.
com/brochure.php
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 The TAP Signals

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 Top-Level View of the TAP Controller

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12/03/24
Linear-Feedback Shift Register (LFSR)

R R R
S0 S1 S2

1 0 0
0 1 0
1 0 1
1 1 0
1 1 1
0 1 1
0 0 1
1 0 0
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 Built-in Logic Block Observation (BILBO)
D0 D1 D2
B0

B1
ScanOut
ScanIn
R R R
S0 S1 S2

B0 B1 Operation mode
1 1 Normal
0 0 Scan
1 0 Pattern generation or signature analysis
0 1 Reset [©Prentice Hall]
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 BILBO – Pattern Generation
D0=1 D1=1 D2 =1
B0=1

B1=0
ScanOut
ScanIn
R R R
S0 S1 S2

B0 B1 Operation mode
1 0 Pattern generation or signature analysis
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BILBO – Pattern Generation vs.
Signature Analysis
 In addition to the BILBO circuit shown in two slides ago,
you may need some extra logic
(e.g., multiplexers) that send either Di’s or 1’s
 Pattern generation
 simple LFSR
 Signature analysis
 Complex
 But we can simulate and predict the correct values

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 BILBO Application
Scan in
BILBO 1

BILBO 2

BILBO 3

BILBO 4

BILBO 5
in out
Comb Comb Comb Comb
Logic 1 Logic 2 Logic 3 Logic 4

Scan out
 Operation:

Seed sent in using the scan chain
 Even BILBOs operate in pattern gen mode, odd ones in signature

analysis

After a complete cycle (or desired # of cycles), odd BILBO values
read through scan out
 The same process repeats, this time with even BILBOs in

signature analysis, odd ones in pattern generation

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 Typical application

DUT-1
DUT-1 DUT-2
DUT-2

Bilbo-1 (generates
Bilbo-1 (generates Bilbo-2
Bilbo-2
pseudo-random
pseudo-random test (compresses
(compresses
patterns) response)
test patterns) response)

Compressed response shifted out of Bilbo-2 & compared

to known „golden“ reference response.
Roles of Bilbo-1 and 2 swapped for testing DUT-1

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 Self-test

(Sub)-Circuit

Stimulus Generator Under Response Analyzer

Test

Test Controller

Rapidly becoming more important with increasing

chip-complexity and larger modules
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 Memory Self-Test
Data in
Data out
Memory Signature
FSM
Under Test Analysis
Address &
R/W Ctrl

Patterns: Writing/Reading 0s, 1s,

12/03/24 [©Prentice Hall]

 Summary
– Test
• Fault model
• TPG (Test Pattern Generation)
• Application of test patterns
• Checking the results
• Fault coverage
• Fault simulation for computing coverage
– Design for Test (DFT)
• Scan path, Boundary scan
• Signature analysis,
• Pseudo random patterns, BILBO

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 References
1. Principles of CMOS VLSI Design -
Weste and Eshraghian, Pearson
Education,
2. Digital Integrated Circuits - John M.
Rabaey, PHI,
3. Essentials of VLSI circuits and
systems – Kamran Eshraghian,
Eshraghian Dougles and A. Pucknell,
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Thank You
………………
12/03/24
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Remember that you are indebted to life until
you help some less fortunate person, just
as you were helped…..
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12/03/24
 How do we guard the sense of value?
We can do so by three things..

1) By constant discrimination between

the real and the unreal..
2) By keeping ourselves busy doing
those things that we have decidedly
accepted as beneficial..
3) By avoiding idle curiosity about the
things which do not concern our main
pursuit in our life….
12/03/24
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