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ASIC
ASIC
AN
AN INTRODUCTION
INTRODUCTION

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Dr Priya Singh
Cambridge institute
of technology
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ASIC VS STANDARD IC
 Standard ICs – ICs sold as Standard Parts
 SSI/LSI/ MSI IC such as MUX, Encoder, Memory Chips, or

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Microprocessor IC
 Application Specific Integrated Circuits

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(ASIC) – A Chip for Toy Bear, Auto-Mobile Control Chip,
Different Communication Chips [ GRoT: ICs not Found in
Data Book]
 Concept Started in 1980s
 An IC Customized to a Particular System or Application –
Custom ICs
 Digital Designs Became a Matter of Placing of Fewer CICs
or ASICs plus Some Glue Logic
 2
Reduced Cost and Improved Reliability
 Application Specific Standard Parts
(ASSP) – Controller Chip for PC or a Modem
BASIC TERMS FOR ASICS
 Full-Custom ICs/Fixed ASICs and Programmable

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ASICs
 Wafer : A circular piece of pure silicon

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 Wafer Lot: 5 ~ 30 wafers, each containing hundreds of
chips(dies) depending upon size of the die
 Die: A rectangular piece of silicon that contains one IC
design
 Mask Layers: Each IC is manufactured with successive
mask layers(10 – 15 layers)
 First half-dozen or so layers define transistors

3
Other half-dozen or so define Interconnect
TYPES OF ASICS – CONT’D
CONT’D

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ASICs

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Semi-Custom
Full-Custom ASICs
ASICs

Stnadard-Cell Gate-Array based Praogrammable

based ASICs ASICs ASICs

PLDs FPGA

• Full-Custom
4 ASICs: Possibly all logic cells and all mask layers customized
• Semi-Custom ASICs: all logic cells are pre-designed and some (possibly all)
mask layers customized
TYPES OF ASICS – CONT’D
CONT’D
Full-Custom ASICs

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 Include some (possibly all) customized logic cells
 Have all their mask layers customized
 Full-custom ASIC design makes sense only

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 When no suitable existing libraries exist or
 Existing library cells are not fast enough or
 The available pre-designed/pre-tested cells consume too much power that a
design can allow or
 The available logic cells are not compact enough to fit or
 ASIC technology is new or/and so special that no cell library exits.
 Offer highest performance and lowest cost (smallest die size) but at the
expense
5 of increased design time, complexity, higher design cost and higher
risk.
 Some Examples: High-Voltage Automobile Control Chips, Ana-Digi
Communication Chips, Sensors and Actuators
TYPES OF ASICS – CONT’D
CONT’D
 Semi-Custom ASICs

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 Standard-Cell based ASICs
(CBIC- “sea-bick”)
 Use logic blocks from

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standard cell libraries, other
mega-cells, full-custom blocks,
system-level macros(SLMs),
functional standard blocks
(FSBs), cores etc.
 Get all mask layers
customized- transistors and
interconnect
 Manufacturing lead time is
around 8 weeks
6  Less efficient in size and
performance but lower in design
cost
TYPES OF ASICS – CONT’D
CONT’D
 Semi-Custom ASICs – Cont’d

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 Standard-Cell based ASICs
(CBIC- “sea-bick”) – Cont’d

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TYPES OF ASICS – CONT’D
CONT’D
 Semi-Custom ASICs – Cont’d

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 Gate Array based ASICs

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TYPES OF ASICS – CONT’D
CONT’D
 Semi-Custom ASICs – Cont’d

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 Gate Array based ASICs - Cont’d

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TYPES OF ASICS – CONT’D
CONT’D
 Semi-Custom ASICs – Cont’d

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 Programmable ASICs
 PLDs - PLDs are low-density devices
which contain 1k – 10 k gates and are

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available both in bipolar and CMOS
technologies [PLA, PAL or GAL]
 CPLDs or FPLDs or FPGAs -
FPGAs combine architecture of gate arrays
with programmability of PLDs.
Programmable gate array and programmable
interconnects.
User Configurable
 Contain Regular Structures -
circuit elements such as AND, OR,
NAND/NOR gates, FFs, Mux, RAMs,
10 Allow Different Programming
Technologies
 Allow both Matrix and Row-
based Architectures
TYPES OF ASICS – CONT’D
CONT’D
 Semi-Custom ASICs – Cont’d

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 Programmable ASICs - Cont’d
 Structure of a CPLD / FPGA

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ASIC
ASIC DESIGN
DESIGN PROCESS
PROCESS

S-1 Design Entry: Schematic entry

or HDL description

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S-2: Logic Synthesis: Using
Verilog HDL or VHDL and
Synthesis tool, produce a netlist-
logic cells and their interconnect

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detail
S-3 System Partitioning: Divide a
large system into ASIC sized pieces
S-4 Pre-Layout Simulation: Check
design functionality
S-5 Floorplanning: Arrange netlist
blocks on the chip
S-6 Placement: Fix cell locations in
a block
S-7 Routing: Make the cell and
block interconnections
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S-8 Extraction: Measure the
interconnect R/C cost
S-9 Post-Layout Simulation
ASIC CELL LIBRARY

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 The cell library is the key part of ASIC design. For a programmable ASIC the FPGA company
supplies you with a library of logic cells in the form of a design kit , you normally do not have a
choice, and the cost is usually a few thousand dollars.
 For MGAs and CBICs you have three choices:

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 the ASIC vendor (the company that will build your ASIC) will supply a cell library,
 or you can buy a cell library from a third-party library vendor ,
 or you can build your own cell library.
 The first choice, using an ASIC-vendor library , requires you to use a set of design tools approved
by the ASIC vendor to enter and simulate your design. An ASIC vendor library is normally
a phantom library. the cells are empty boxes, or phantoms , but contain enough information for
layout . After you complete layout you hand off a netlist to the ASIC vendor, who fills in the empty
boxes ( phantom instantiation ) before manufacturing your chip.
 The second and third choices require you to make a buy-or-build decision . If you complete an ASIC
design using a cell library that you bought, you also own the masks (the tooling ) that are used to
manufacture your ASIC. This is called customer-owned tooling
 The third choice is to develop a cell library in-house. Many large computer and electronics
companies make this choice. Most of the cell libraries designed today are still developed in-house
despite the fact that the process of library development is complex and very expensive.
 However created, each cell in an ASIC cell library must contain the following:
 A physical layout , A behavioral model , A Verilog/VHDL model , A detailed timing model , A test
strategy , A circuit schematic , A cell icon , A wire-load model , A routing model
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ASIC CELL LIBRARY

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 For MGA and CBIC cell libraries we need to
complete cell design and cell layout .

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 The ASIC designer may not actually see the

layout if it is hidden inside a phantom, but

the layout will be needed eventually. In a
programmable ASIC the cell layout is part of
the programmable ASIC design

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 The ASIC designer needs a high-
level, behavioral model for each cell because
simulation at the detailed timing level takes too

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long for a complete ASIC design.

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 For a NAND gate a behavioral model is simple.

 A multiport RAM model can be very complex.

 The designer may require Verilog and VHDL

models in addition to the models for a

particular logic simulator.

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 ASIC designers also need a detailed timing model for each cell to
determine the performance of the critical pieces of an ASIC. It is
too difficult, too time-consuming, and too expensive to build every
cell in silicon and measure the cell delays.

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 Instead library engineers simulate the delay of each cell, a process
known as characterization . Characterizing a standard-cell or gate-
array library involves circuit extraction from the full-custom cell
layout for each cell.

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 The extracted schematic includes all the parasitic resistance and
capacitance elements. Then library engineers perform a simulation
of each cell including the parasitic elements to determine the
switching delays.
 The simulation models for the transistors are derived from
measurements on special chips included on a wafer called process
control monitors ( PCMs ) or drop-ins . Library engineers then use
the results of the circuit simulation to generate detailed timing
models for logic simulation

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 All ASICs need to be production tested (programmable ASICs may
be tested by the manufacturer before they are customized, but
they still need to be tested). Simple cells in small or medium-size
blocks can be tested using automated techniques, but large blocks

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such as RAM or multipliers need a planned strategy.
 The cell schematic (a netlist description) describes each cell so
that the cell designer can perform simulation for complex cells. You

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may not need the detailed cell schematic for all cells, but you need
enough information to compare what you think is on the silicon
(the schematic) with what is actually on the silicon (the layout)—
this is a layout versus schematic ( LVS ) check.
 If the ASIC designer uses schematic entry, each cell needs a cell
icon together with connector and naming information that can be
used by design tools from different vendors. One of the
advantages of using logic synthesis rather than schematic design
entry is eliminating the problems with icons, connectors, and cell
names. Logic synthesis also makes moving an ASIC between
different cell libraries, or retargeting , much easier.

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 In order to estimate the parasitic capacitance of wires before
we actually complete any routing, we need a statistical
estimate of the capacitance for a net in a given size circuit

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block.
 This usually takes the form of a look-up table known as a wire-
load model . We also need a routing model for each cell. Large

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cells are too complex for the physical design or layout tools to
handle directly and we need a simpler representation—
a phantom —of the physical layout that still contains all the
necessary information.
 The phantom may include information that tells the automated
routing tool where it can and cannot place wires over the cell,
as well as the location and types of the connections to the cell.

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