University Institute of Computing

Bachelor of Computer Applications

Digital Circuits & Logic Designs
Sub Code: 20CAT112

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 Syllabus
UNIT-III

Sequential Circuits: Flip Flops: S-R, J-K, T, D, master-slave, edge triggered, shift registers, sequence
generators, Counters, Asynchronous and Synchronous Ring Counters and Johnson Counter, Design of
Synchronous and Asynchronous sequential circuits
.
 Course Outlines

1) Flip Flops
2) Types of Flip Flops
3) S-R Flip Flop
4) Clocked SR Flip Flop
5) Applications
6) FAQs

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 Learning Outcomes

After this lecture :

• Student will learn what are flip flops.

• Student will learn various types of flip flops.

• Student will able to know the SR flip flop and its applications.

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 Flip Flops
• A flip-flop is a device which stores a single bit (binary digit) of data;
one of its two states represents a "one" and the other represents a
"zero".
• Flip-flops are used as data storage elements.
• Flip-flops can be either simple (transparent or asynchronous) or
clocked (synchronous).
• In the context of hardware description languages, the simple ones are
commonly described as latches, while the clocked ones are described
as flip-flops.
Difference between Latches and Flip Flops
 Types of Flip Flops

S-R F/F
1

J-K F/F
2
Flip Flops

3 D F/F

4 T F/F
 S-R Flip Flops
• S-R flip-flop stands for SET-RESET flip-flops.
• The SET-RESET flip-flop consists of two NOR gates and also two NAND
gates.
• These flip-flops are also called S-R Latch.
• The design of these flip flops also includes two inputs, called the SET
[S] and RESET [R]. There are also two outputs, Q and Q’.
• In the context of hardware description languages, the simple ones are
commonly described as latches, while the clocked ones are described
as flip-flops.
S-R Flip Flop (Symbol)

Fig 1: Symbol of SR Flip Flop

S-R Flip Flop using NAND Gate

Fig 2: SR Flip Flop using NAND Gate

Other representation and Truth Table of S-R Flip Flop

Fig 3 : RS flip using NOR Gate

 Clocked SR Flip Flop

A flip-flop circuit that is set and reset at specific times by adding clock pulses to the input so
that the circuit is triggered only if both trigger and clock pulses are present simultaneously.

Fig 4 : Clocked SR flip flop (Symbol and Circuit)

Truth Table of Clocked SR Flip Flop

Fig 5 : Truth Table of Clocked SR flip flop

 Drawback of S-R Flip Flops
• The one major disadvantage of the s-r flip flop is that in the condition
when the clock is triggered the inputs become high which is an
undesirable condition because it causes invalid input ,the condition in
which you can't predict the output.
• In SR FF we can apply 1 to both S and R inputs. This will give
unpredictable output. This is because both the output NAND gate will
try to change it state and one who will win the race will remain in that
state making others to compliment it. But there will be race between
both NAND gates and hence it's called race condition which is avoided
or marked as forbidden.
 J-K Flip Flop
• The JK Flip Flop is the most widely used flip flop. It is considered to be
a universal flip-flop circuit. The sequential operation of the JK Flip Flop
is the same as for the RS flip-flop with the same SET and RESET input.

• The difference is that the JK Flip Flop does not have the invalid input
states of the RS Latch (when S and R are both 1). The JK Flip Flop
name has been kept on the inventor name of the circuit known
as Jack Kilby.
 Issues in RS flip flop
• The basic NAND gate RS flip-flop suffers from two main problems.
• Firstly, the condition when S = 0 and R = 0 should be avoided.
• Secondly, if the state of S or R changes its state while the input which
is enabled is high, the correct latching action does not occur.
• Thus to overcome these two problems of the RS Flip-Flop, the JK Flip
Flop was designed.
 Why JK flip flop?
• The JK Flip Flop is basically a gated RS flip flop with the addition of the
clock input circuitry. When both the inputs S and R are equal to logic
“1”, the invalid condition takes place.
• Thus, to prevent this invalid condition, a clock circuit is introduced.
The JK Flip Flop has four possible input combinations because of the
addition of the clocked input. The four inputs are “logic 1”, ‘logic 0”.
“No change’ and “Toggle”.
J-K Flip Flop (Symbol)

Fig 1: Symbol of JK Flip Flop

J-K Flip Flop

Fig 2: JK Flip Flop circuit using NAND Gate

Truth Table of JK Flip Flop

Fig 3 : Truth Table of JK flip flop

 Drawback of JK Flip Flop

• JK flip-flop has a drawback of timing problem known as “RACE”. The condition of RACE arises if
the output Q changes its state before the timing pulse of the clock input has time to go in OFF
state.

• The timing pulse period (T) should be kept as short as possible to avoid the problem of timing.

• This condition is not possible always thus a much-improved flip-flop named Master Salve JK
Flip Flop was developed. This eliminates all the timing problems by using two RS flip-flop
connected in series. One is for the “MASTER “ circuit, which triggers on the leading edge of the
clock pulse. The other is called the “SLAVE” circuit, which triggers when the clock pulse is at
the falling edge.
 Master Slave flip flop

• The Master-Slave Flip-Flop is basically a combination of two JK flip-flops

connected together in a series configuration. Out of these, one acts as
the “master” and the other as a “slave”. The output from the master flip flop is
connected to the two inputs of the slave flip flop whose output is fed back to
inputs of the master flip flop.

• In addition to these two flip-flops, the circuit also includes an inverter. The
inverter is connected to clock pulse in such a way that the inverted clock pulse is
given to the slave flip-flop. In other words if CP=0 for a master flip-flop, then
CP=1 for a slave flip-flop and if CP=1 for master flip flop then it becomes 0 for
slave flip flop.
Master Slave J-K flip flop

Fig 4 : Master Slave flip flop Circuit

 Working of Master Slave flip flop

1.When the clock pulse goes to 1, the slave is isolated; J and K inputs may affect the state of the
system. The slave flip-flop is isolated until the CP goes to 0. When the CP goes back to 0,
information is passed from the master flip-flop to the slave and output is obtained.
2.Firstly the master flip flop is positive level triggered and the slave flip flop is negative level
triggered, so the master responds before the slave.
3.If J=0 and K=1, the high Q’ output of the master goes to the K input of the slave and the clock
forces the slave to reset, thus the slave copies the master.
4.If J=1 and K=0, the high Q output of the master goes to the J input of the slave and the
Negative transition of the clock sets the slave, copying the master.
5.If J=1 and K=1, it toggles on the positive transition of the clock and thus the slave toggles on
the negative transition of the clock.
6.If J=0 and K=0, the flip flop is disabled and Q remains unchanged.
Timing Diagram of a Master Slave flip flop

Fig 5 : Timing Diagram of Master Slave flip flop

 Applications of flip flops

There are various types of flip-flops being used in digital electronic circuits and the
applications of Flip-flops are as specified below.

• Counters
• Frequency Dividers
• Shift Registers
• Storage Registers
• Bounce elimination switch
• Data storage
• Data transfer
• Latch
• Registers
• Memory
 Frequently Asked Questions
Q1: What is the difference between SR and JK flip flop?
Q2: What is the drawback of JK flip flop.
Q3: How JK is different from Master Slave JK flip flop?
Q4: Mention the solution to overcome the drawback of JK flip flop.

ales
 References
• https://www.daenotes.com/electronics/digital-electronics/flip-flops-typ
es-applications-woking
• https://www.javatpoint.com/s-r-flip-flop
• https://circuitglobe.com/jk-flip-flop.html
• https://www.geeksforgeeks.org/master-slave-jk-flip-flop/
THANK YOU