WELCOME

TO
THE WORLD OF VLSI

1
VERY LARGE SCALE INTEGRATION

Is the science of integrating millions of transistors

on a Silicon Chip.

2
 First things First
 Learn to Differentiate between, Domain and Platform.

 VLSI is the Platform that you use to implement various domains.

i.e. VLSI Techniques that you know / learn are Platform

knowledge.

 Networking / DSP/ PCI/USB …etc are domains, which are

implemented using one of the many platforms available.
Note : VLSI is one of the Platforms.

 Eg. DSP can be implemented using

“C” and PC, DSP P or Programmable Logic
3
VLSI IN INDUSTRY AN EXAMPLE

4
 EVOLUTION IN COMPUTERS

First Computer (ENIAC)

5
 WHERE DID IT BEGIN
 New York Times

“ A device called a transistor, which has

several applications in radio where a
vacuum tube ordinarily is employed, was
demonstrated for the first time yesterday at
Bell Telephone Laboratories, 463 West
Street, where it was invented. ”

23rd December 1947

John Bardeen Walter Brattain William Shockley
6
 HISTORY OF IC DESIGN
 Date - 28th July.
 Year - 1958.
 Components – 1-Transistor, 3-Resistors,
1-Capacitor.

 Jack Kilby assembled those components

together on one semiconductor. The world’s
first integrated circuit.
 Jack did more than invent the integrated
circuit that day.
 Jack Kilby invented the FUTURE
 He received the noble Prize for this invention
in October 2000.

7
 HISTORY OF IC DESIGN
 The first commercial monolithic IC came in the market in 1961.
 It was a Flip-Flop, with 2 Transistors & resistor
 Cost~$100

 The metal-oxide-semiconductor (MOS) IC in 1962.

 The complementary MOS (CMOS) IC in 1963.

8
 MOORE’S LAW
 In 1969, Gorden Moore stated that, the number of transistors per
chip will double every 18 months !!!

 And it is happening !!!!!!!

 Now Moore's law has become self sustaining.

 Infact our world follows Moore’s Law.

9
 EVIDENCE OF MOORE’S LAW
ACCORDING TO GORDEN MOORE -

YEAR 1996 MID 1997 1999 MID 2000

5 10 20 40
(in millions)

Pentium-I Came In 1996 Transistor Count – 5 Million

Pentium-IV Came In 2001 Transistor Count – 43 Million

10
THE PROJECTED TREND OF IC DEVICES

IC technology 1987 1992 2000

TTL 12% 4% 1%

ECL 4% 2% Less than 1%

PMOS Less than 1% 0% 0%

NMOS 24% 4% Less than 1%

CMOS 39% 73% 82%

BICMOS 0% 2% 6%

GaAs Less than 1% Less than 1% 1%

How are we concerned ??

11
MOS STRUCTURE &
FUNCTIONALITY

12
 WHY CMOS ??
 Consumes no Static Power.
.
 High input impedance

 Has the highest Noise immunity.

 Supply Voltage tolerant –

 Voltage required to switch gate is fixed percentage of VDD.
 Fully restored logic level : Output settles at VDD or Vss

13
 IC COMPLEXITY
 Is measured in terms of no. of logic
gates and transistors.

 Gate implies a 2-i/p NAND gate i.e.

100K-gate IC contains an equivalent
of 100,000 2-i/p NAND gates. 1
 Note: 4-MOS Transistors in a 2-i/p NAND
gate.
Why NAND Gates?

GND

14
 NAND GATE VS NOR GATE
 2-Input NAND gate 2-input NOR gate
 Why is NAND gate an universal gate ?

Hint : SIZE is imp

15
 POWER DISSIPATION IN CMOS
The 3- most important constraints of IC Design are
Speed, Power and Area

Power is related as follows:-

P = FCV 2

 where,
 C = Capacitance
 V = Supply voltage
 F = Clock frequency
Why is the LOAD modeled as a capacitance ?
16
 POWER DISSIPATION IN CMOS
CMOS INVERTER

POWER= ½ CV 2 + ½ CV 2
= CV 2 --
IN ONE CYCLE

So for F CYCLES power dissipation is FCV 2

17
 Where Does Power Go in CMOS?
 Dynamic Power Consumption
 Charging and Discharging Capacitors

 Short Circuit Currents

 Short Circuit Path between Supply Rails during Switching

 Leakage currents
 Leaking diodes and transistors

18
WHY WORRY ABOUT POWERPortability
?

Battery industry does not have a Gordon Moore

19
Voltage Scaling

 What is the motivation for reducing Voltage ??

Hint – feature Size

 What is the sweet side effect of Voltage scaling ?

Hint – P = FCV2

 Any other sweet side effect of Voltage scaling ?

Hint – slew rate limitation

20
Process Technology and Supply
Voltage

21
 VLSI - RECENT DEVELOPMENTS
 Nanometer technology 0.5u, 0.35u, 0.25u, 0.18u, 0.13u, 90nm,
65 nm ….
 Device Operating Speeds - Crossing Giga Hz.
 Operating Voltage Migration - 5V, 3.3V, 2.5V, 1.8V, 1.5V, 1V …
 Large number of transistors per die - presently more than 300
million transistors

22
 VLSI CHIPS PRESENT & FUTURE

Year Millions of Die size Voltage Power Clock rate Feature size
transistors [ mm2 ] [V] [W] [ MHz ] [ um ]
[ per cm2 ]

1997 - 4-10 50-385 1.2-2.5 1.2-61 200-730 0.25-0.15

2000

2003 - 18-39 60-520 0.9-1.5 2-96 530-1100 0.13-0.10

2006

2009 - 84-180 70-750 0.5-0.9 2.8-109 840-1830 0.07- 0.05

2012

23
EVOLUTION OF PROCESSORS

Processor 4004 8008 8080 8086 8088

Introduced 11 / 15 / 71 4 / 1 / 72 4 / 1 / 74 6 / 8 / 78 6 / 1 / 79

Clock 108 KHz 200 KHz 2 MHz 5 MHz, 8 MHz, 5 MHz, 8

Speeds 10 MHz MHz

Bus Width 4 bits 8 bits 8 bits 16 bits 8 bits

Number of 2,300 3,500 6,000 29,000 29,000

Transistors (10 µ) (10 µ) (6 µ) (3 µ) (3 µ)

24
EVOLUTION OF PROCESSORS

Processor 80286 Intel 386 DX Intel 386 SX Intel 486

DX CPU
Introduced 2 / 1 / 82 10 / 17 / 85 6 / 16 / 88 4 / 10 / 89

Clock Speeds 6, 8, 10, 12.5 16, 20, 25, 16, 20, 25, 25, 33, 50 MHz
MHz 33 MHz 33 MHz
Bus Width 16 bits 32 bits 16 bits 32 bits

Number of 134,000 275,000 75,000 1.2 million

Transistors (1.5 µ) (1 µ) (1 µ) (1 µ)
( .8 µ @ 50MHz)

25
 EVOLUTION OF PROCESSORS
Processor Intel 486 SX Pentium Pentium Pro Pentium II
Introduced 4 / 22 / 91 3 / 22 / 93 11 / 01 / 95 5 / 07 / 97

Clock 16, 20, 60, 66 MHz 150, 166, 180, 200, 233, 266,
Speeds 25, 33 MHz 200 MHz 300 MHz

Bus Width 32 bits 64 bits 64 bits 64 bits

Number of 1.185 million 3.1 million 5.5 million 7.5 million

Transistors (1 µ) (.8 µ) (0.35 µ) (0.35 µ)

Latest CPUs have more than 300 million transistors and use
65nm technology.

26
The First Computer

The Babbage Difference Engine

(1832)
25,000 parts
Cost : £17,470

27
ENIAC - The first electronic computer (1946)

28
HOW DOES IT LOOK LIKE
TODAY ?

29
PENTIUM® III DIE - 0.18µ
TECHNOLOGY

How
does
this
picture
affect
us. ?
30
SILICON WAFER
 A single silicon wafer
holds many dies.

 Wafer specifications
Thickness - 300 µ
Diameter - 8 inches.

 New fabs use 12”

Diameter

31
MULTI LAYER METALLISATION

• Advanced fabrication techniques like multi layer metallization are

needed to achieve the large transistor density in small packages
32
 APPROXIMATE SIZE RELATIONSHIP

Processor Transistors Processor Transistors

8085 6 µ 6,000 P-I 0.5 µ 5.5 million

8086 3 µ 29,000 P-II 0.35 µ 7.5 million

33
What is the end product ?

VLSI

34
 VLSI- Advantages
 Integration improves the design:
 lower parasitic’s = higher speed;
 lower power;
 physically smaller.
 Integration reduces manufacturing cost-(almost) no manual
assembly.

35
 ADVANTAGES OF VLSI
 Reduction in  Increase in
 Design cycle time  Operating Speed
 Product Size  Design Security
 Power Consumption  Productivity
 Cost  Design Flexibility

36
 VLSI Design
ISSUES CHALLENGES
 Design Methodology  Rate of change of technology Vs
 Design cycle time
Time To Market
 Clock Speed  Feature Size Vs Modeling &
 Power Consumption Testing
 Cost
 Silicon Technology  Speed Vs Power

37
 THE GOAL OF IC DESIGNER
 Meet the market requirement
 Satisfying the customers needs
 Beating The competition
 Increasing the functionality
 Reducing the cost
 Achieved By
 Using the next generation Silicon Technologies
 New Design Concepts & Tools
 High Level Integration

38
VLSI - FAMILY IN THE PRESENT DAY
CONTEXT

 VLSI family consists of Any thing special

 PLD’s about this guy
 ASIC’s
 Full Custom devices
 EDA Tools.
 IP Cores – Soft IC’s

Explosion in Technology in all the above has changed the

VLSI Design scenario.

39
 WHAT IS PROGRAMMABLE LOGIC ?
 Programmable Logic Consists of,

 Simple Programmable Logic Devices (SPLDs)

 Complex Programmable Logic Devices (CPLDs)

 Field Programmable Gate Arrays (FPGAs)

40
 PROGRAMMABLE LOGIC DEVICES
 Programmable logic device is a predefined architecture which
consists of
 Configurable logic [ flip-flop, Combinational logic, embedded logic ].
 Programmable interconnects : Defines the interconnection within
the configurable logic as well as to the input-output block.
 Input output blocks.

 PLD’S can be broadly classified as

 Complex Programmable Logic Devices [ CPLD]
 Field Programmable Gate Array [ FPGA ]

41
 A BIT OF HISTORY
 PAL (programmable array logic) device and PALASM design
software, were conceived of and developed in the 1978 at
Monolithic Memories, Inc, by
 John Birkner H. T. Chua.

This was the development which launched today’s $3.7 billion

programmable logic industry.
Their invention got the U.S. patent number 4,124,899
42
 Complex Programmable Logic
Devices
 Complex Programmable Logic Devices.
 Also called as EPLD, PEEL, MAX by diff. Vendors.
 Non volatile , PROM based devices.
 Having a structure with 2 to 64 PAL like structures, each
containing one Flip-Flop.
 Have continuous interconnect structure, so delays are
predictable.
 Having types which uses configuration memory types like
EPROM ,EEPROM , FLASH.

43
 FIELD PROGRAMMABLE GATE
ARRAY
 At the heart is a regular array of
programmable basic logic cells
that can implement combinational
as well as sequential logic (flip-
flops).
 A matrix of programmable
interconnect surrounds the basic
logic cells.
 Programmable I/O cells surround
the core.
 Design turnaround is a few hours.

44
 TRENDS IN PLD’S

Year Device Introduced By Features

Monolothic Memories
1970 PAL
Inc.

1984 EPLD-EP300 Altera

1985 XC2064 Xilinx 800 gates, 2.0μ, $55

FPGA-
1988 Xilinx 10K gates
XC3000

1988 MAX5000 Altera 10K gates

45
 TRENDS IN PLD’S
Year Device Introduced By Features
1991 pASIC-1 Quick Logic Embedded RAM, lower cost
AT&T 20K gates, 0.8μ, 2-layer
1992 ORCA
Microelectronics metal.
1995 pASIC2 Quick Logic Embedded PCI Core
1997 pASIC3 Quick Logic Embedded DSP Core
Spartan, 1M gate , Voltage Migration
1998-99 Xilinx
Virtex from 2.5 to 1.8
Spartan3 Upto 20M gates, 90 Nm
2004-05 Xilinx
Virtex4 Voltage migration to 1.2V
More than 20M gates, 65
2006-07 Virtex5 Xilinx nM
Voltage migration to 1V

46
Programmable Logic Market share.

Year – 2004, Total sales of programmable devices ~ $3.7-Billion

Xilinx, Altera, Actel, Lattice, Quick Logic, Atmel …others
47
48
 WHAT ARE ASICS..?
 ASICs are silicon chips that have been designed for a specific
application. Putting in other words, it is a chip designed to perform a
particular operation as opposed to general purpose integrated circuits:

 An ASIC is NOT software programmable to perform different tasks.

 ICs that are not ASICs are :

 DRAM, SRAM, 8085 Silicon Die

 ICs which are ASICs:

 Baseband processor in mobile phone
 Chipsets in PCs
 MPEG encoders/ decoders
 DSP functions in hardware, e.g. FFT

49
 WHY USE ASICs?
 Requirements :
 Greater Complexity, Increased Performance
 Higher Density, Lower Power Dissipation
 Shorter Time-to-Market (TTM)
 Cheaper in large quantaties

 ASIC’s can be broadly classified as

 Full custom ASIC
 Semi custom ASIC
 Gate Array based ASIC
 Programmable ASIC ( PLD’S )

50
 FULL CUSTOM ASIC
 When engineers have a specific application to be designed and they
are bothered about the performance, speed, power and cost, they go
for designing Full Custom ASIC.

 The circuit is partitioned into a collection of sub-circuits according to

some criteria such as functionality. Which are laid out specifically for
one chip.

 Every transistor is designed and drawn by hand.

 Typically only way to design analog portions of ASICs.

 Usually used for layout of microprocessors.

 Full-custom design is very time consuming; thus the method is

inappropriate for very large circuits, unless performance is of utmost
importance
51
 SEMI CUSTOM ASIC
 All mask layers are customized - transistors and interconnect
 Automated buffer sizing, placement and routing
 Custom blocks can be embedded
 Manufacturing lead time is about eight weeks.

52
 EDA TOOLS THE THIRD ARM
 EDA - stands for Electronic design Automation

 EDA Tools are the software programs that make the design flow
happen.
e.g. Simulator, Synthesizer, Schematic Editor …etc

 EDA tools are the most important aspects of VLSI Design and in
the present day context, VLSI design is totally dependent upon
EDA Tools.

53
 BACKBONE OF VLSI DESIGN
Backbone of VLSI design are, Industries
like….
EDA Companies
 Mentor Graphics
 Synplicity
 Synopsys
 Cadence
 Aldec……

Device Vendors
 Xilinx, Altera , Actel, Cypress,
QuickLogic …etc

54
 EDA TOOLS: Design Entry
 VIEWlogic – a ( ViewDraw - a hierarchical schematic capture
» and block diagram tool)
 Mentor Graphics ( Renoir )
 Cadence Design Systems
 OrCAD
 ALDEC ( Active-HDL )
 Simucad ( Silos-3 )
 Protel
 Tanner Research ( L-Edit Pro 8.4 )
 Capilano Computing Systems ( DesignWorksTM )
 Capfast Morphologic ( rapid-development system )
 MyCAD
55
 EDA Tools :Design Simulation
 Mentor Graphics ( Modelsim )
 Synopsys
 VCS™ ( High performance Verilog Simulation )
 Sirocco™ ( High performance VHDL Simulation )
 Cadence
 - Verilog XL Simulator
 - DRACULA - The Physical Verification Standard
 Simucad ( Silos-III )
 SynaptiCAD - TestBencher Pro - Timing Diagram & Testbench
Generation Software
 Quickturn Design Systems ( PowerSuite™ )
 VIEWlogic ( Fusion/SpeedWave - a VHDL simulator)
 Diagonal Systems ( BestBench )
56
 EDA TOOLS : Logic Synthesis &
Optimization
 Synopsys
 FPGA Express
 FPGA Compiler
 Synplicity – ( Synplify )
 Mentor Graphics - ( LeonardoSpectrum )
 VIEWlogic – ( IntelliFlow )
 Cadence Design Systems
 Aldec – ( ACTIVE synthesis )
 Accolade Design Automation
 Logical Devices

57
 Programmable Logic Vendors
 Xilinx - Spartan II, Saprtan3, Virtex-II, Virtex-IIPro, Virtex4
( Software : ISE 8.1i )
 Altera - FLEX, APEX, MAX, Cyclone, CycloneII, Stratix
( Software : Quartus II, MAX+II )
 Lattice - ispEXPERT Compiler
 Actel - Actel's Designer Series FPGA Development System
 Atmel - FPGA Integrated Development System (IDS)

58
 WHAT IS CORE ?
 Are also called as IP-Cores.
 They are big business and a hot
issue.
 They can be looked upon as “Soft
IC’s”.
 They Reduce Time for Design &
Verifications

 Are Optimized by Device vendors,

 Hence offer Best possible
Device utilization
 Help achieve,

Better Overall System

Performance
Fast Time To Market

59
 IP Cores

Defining IP
 Pre designed modules are called Intellectual Property (IP) Cores or Virtual
Components (VC)
 Main concept is reuse of existing designs
 IP cores allow design teams to rapidly create large system-on-a-chip designs
(SOCs) by integrating pre-made blocks that do not require any design work or
verification
 IP cored reduce the possibility of failure based on design and verification of a
block for the first time

Why IP’s???
 Savings in time and cost to produce more complex designs when using third-
party IP cores
 Ease of integration for available IP cores into more complicated systems
 Commercially available IP cores are pre-verified and reduce the design risk
 Significant improvement to the product design cycle

60
 IP Core Categories
IP Cores

Firm Cores
Hard Cores Soft Cores

Hard IP Cores
 Hard IP cores consist of hard layouts using particular physical design libraries
and are delivered in masked-level designed blocks
 These blocks are designed to be as efficient as possible in terms of power
consumption, silicon real estate and performance
 Hard cores offer optimized implementation and the highest performance for
their chosen physical library
 Integration of hard IP cores is quite simple and the core can be dropped into an
SOC physical design with minor integration effort
 However, hard cores are technology dependent and provide minimum flexibility
and portability in reconfiguration and integration across multiple designs and
technologies
 A hard core is very technology-specific
61
 IP Core Categories - Soft IP Cores
 Soft IP cores are delivered as RTL VHDL/ Verilog code to provide
functional descriptions of IPs
 These cores offer maximum flexibility and re-configurability to match
the requirements of a specific design application
 But these must be synthesized, optimized, and verified by their user
before integration into designs
 It is technology independent. VHDL or Verilog doesn’t require the use
of a specific process technology or standard cell library. This means
same IP can be used for multiple designs
 Soft cores are subsequently synthesized down into a group of PLBs
(possibly combined with some hard IP blocks like multipliers, adders
etc)
 It’s not possible for the provider to support all the potential libraries

62
 IP Core Categories - Firm IP Cores
 Firm IPs balance the high performance and optimization properties of
hard IPs with the flexibility of soft IPs
 These cores are delivered in the form of targeted netlists to specific
physical libraries after going through synthesis without performing the
physical layout
 It also comes in the form of a library of high level functions, but these
functions have already been optimally mapped, placed and routed into
a group of PLBs
 One or more copies of each predefined firm IP block can be
instantiated into the design as required

IP format Representation Optimization Technology Reusability

Hard GDSII (format) Very High Technology Low

Dependent

Soft RTL Low Technology Very High

Independent
Firm Targeted high Technology High
Netlists Generic
63
 IP Sources
 The three main sources of IP are
 Internally created blocks from previous designs
 FPGA vendors
 Third party IP providers (Cast, Virtual IP Group ..etc)
 IP Core Generators- These generators are special tools that act
as IP block/core generators
 IP generators are almost invariably parameterized, allows
designers to specify parameters like depths, widths, or both of
buses and functional elements
 It also allows to select a list of functional elements that designer
wish to include or exclude from final representation
 Helps designer to create the most efficient IP block/core in terms of
its resource requirements and performance

64
 CORE SOLUTIONS APPLICATIONS
 Base Level Functions
Microprocessors, Microcontrollers, UART, Other Peripherals.
 Standard interface - PCI, USB, FIREWIRE, Ethernet MAC …etc,
 DSP Functions - Filters, MAC, FFT, Cordic …etc
 Telecom & Networking - ATM, SONNET…etc

 Xilinx Supplies more than 1000 types of Free cores with their
Software packages.

65
 VLSI
HOW DO YOU DO IT ?

66
 Design Entry text

text text

Functional
Simulation

Synthesis
Gate Level
Simulation

Mapping +
Timing Translation
Simulation

Place & Route

Programming

67
 DESIGN ENTRY
 Design entry is the media through which idea’s with designer are
entered into the soft format.

 There are various ways in which the design can be entered.

Some of the popular one’s are :

 Designing with the help of schematics.

 Designing using HDL’S [ Hardware Description Language ].

 Designing using State Machines.

68
 DESIGN ENTRY
SCHEMATIC HDL CODING FSM “C” “Java”

4 input AND gate

69
 DESIGN ENTRY
 Hardware Description Languages : An effective way to describe
the functionality in a user friendly manner

 VHDL
 [ Very High Speed Integrated Circuit Hardware Description
Language ].
Origin : 1981 (DOD America)
Standard : IEEE1076 –1999

 VERILOG
Standard : IEEE1364

70
 DESIGN ENTRY
SCHEMATIC HDL CODING FSM “C” “Java”
Use library ieee;
use ieee.std_logic_1164.all;
entity AND4 is
port (
A, B, C,D : in std_logic;
S : out std_logic;
);
end AND4 ;
architecture AND4 _ARCH of AND4 is
begin
S <= (A and B) and (C and D) ;
end AND4_ARCH;

71
 DESIGN ENTRY
 SCHEMATIC HDL CODING FSM “C” “Java”

STATE MACHINE TO COUNT THE SEQUENCE

001 - 011 - 111
72
 RTL MODEL
 Register Transfer Level Model : Functionality is described as flow
of data in between the registers

73
 Simulation Purpose
 Analyze a Design / Testbench for Correct Syntax

 Elaborate the Design for Integrity

 Run the Testbench

 Observe that the Design Behaves as Expected

 Saves the time consuming need for physical prototyping

74
 FUNCTIONAL SIMULATION
 Functional Simulation is carried after entering the design.
 Need for the simulation comes from the fact that the entered
design is working as per specifications
 Advantage : Saves the time consuming need for physical
prototyping

A
B

C=1
D=1

75
Functional simulation of 4-input and gate
 SYNTHESIS
 Synthesis is automatic process of converting HDL code into
equivalent logic gates.
 Synthesis results are Target Technology Dependent.
 Works on the principle that any function can be implemented
using NAND.
Use library ieee;
use ieee.std_logic_1164.all;
entity AND4 is
port (
A, B, C,D : in std_logic;
S : out std_logic;
);
end AND4 ;
architecture AND4 _ARCH of AND4 is
begin
S <= (A and B) and (C and D) ;
end AND4_ARCH;
76
SYNTHESIS

Constraint
Design Libraries

Synthesi
s

Netlist
Report

77
Different Implementations of 4-i/p
Gate

78
SYNTHESIS – ADVANTAGE HDL

The code is synthesized into a counter,

Advantages:
• Easy and logical way of describing a counter in HDL.
• Easily scalable architecture.
79
 POST-SYNTHESIS SIMULATION
 Post Synthesis also called as GATE Level Simulation
Simulation verifies functionality after Synthesis.
 Need - Synthesis programs may implement HDL code in different way
than expected.
Post synthesis simulation of 4-input and gate

A
B

C=1
D=1 Models gate
S delays

S1
80
GATE DELAY
 PLACE & ROUTE
 Is the process of,
 Placing the design into the
specified Device.
 Optimizing the usage of
available resources, viz.
logic cells and Interconnects.
 Is Vendor and Target
Technology Dependent
 It Uses
 Vendor Libraries
Vendor ???
 Algorithms
 Directives
 User Specified Constraints

81
4-INPUT AND GATE – AFTER P&R

82
 POST P & R SIMULATION
 Post P&R Simulation verifies functionality after place and route
 Need - Interconnect delays are known at this stage only.

B
C=1
D= 1

S1
S2

GATE DELAY 83
INTERCONNECT DELAY
 Others
PROGRAM & SYSTEM TEST
 Programming is the process of downloading the design into the
device. Applicable only for PLD’s
 After the device is programmed, you are ready to test the actual
system, with real life inputs and outputs.
DESIGN LIBRARIES
 Are pre-Compiled design units. Of standard functions.
 Are stored in a design library.
 Are generally specified by Device Vendors, come as a part of
their package.
 Also Designers can store components designed by them as
library components to achieve design reuse.

84
 VLSI - APPLICATIONS
 VLSI Finds applications in all aspects of Life,
 Consumer Electronics, Defense, Computers, Communication,
Space, Networking…..

 Some of applications could be listed as

 WIRELESS LAN
 RE - CONFIGURABLE COMPUTING
 WEARABLE COMPUTERS
 HOME NETWORKING
 BLUETOOTH
 SONET / SDH
 Bus Interfaces, viz. PCI, Firewire, USB

85
 WIRELESS LAN - NO WIRES
Digital Camera
Computer

Scanner

Inkjet
Printer

Home Audio System PDA Cordless Phone

Cell Phone Base Station
MP3
Player
86
 WIRELESS LAN ON THE ROAD
Car Audio System

PDA
Cell Phone

Headset
Pay Phone
& Access Point

MP3
Player
Hotel Phone
Laptop & Access Point 87
WEARABLE COMPUTERS

88