Microprocessor and Interfacing

(MPI)
GTU # 3160712

Unit-7:
I/O Interfacing
Subject Overview

Sr. No. Unit %

Weightage
1 Introduction to Microprocessor 8%
2 Microprocessor Architecture and Operations 7%
3 8085 Microprocessor 12%
4 Assembly Language Programming Basics 13%
5 8085 Assembly Language Programs 12%
6 Stack & Subroutines 13%
7 I/O Interfacing 10%
8 Advanced Microprocessors 15%
 Looping
Topics to be covered
 Introduction to Interfacing Concepts
 I/O Ports
 Interfacing Of I/O Devices
 Interrupts In 8085
 Programmable Interrupt Controller
8259A
 Programmable Peripheral Interface
8255A
Introduction to
Interfacing Concepts
Introduction to Interfacing Concepts
 Interface is the path for communication between two components.
 Interfacing is of two types, memory interfacing and I/O interfacing.

IO Interfacing
What do you mean by I/O Interfacing?
 There are various communication devices like the keyboard, mouse,
printer, etc.
 So, we need to interface the keyboard and other devices with the
microprocessor by using latches and buffers.
 This type of interfacing is known as I/O interfacing.
8085 Interfacing Pins
Following is the list of 8085 pins used for
interfacing with other devices:
1. A15-A8 (Higher Address Bus)
2. AD7-AD0(Lower Address/Data Bus)
3. ALE
4. RD
5. WR
6. READY
Ways of Communication with Microprocessor
There are two ways of communication in which the microprocessor can
connect with the outside world.
1. Serial Communication Interface
In this type of communication, the interface gets a single bit of data
from the microprocessor and sends it bit by bit to the other system
serially and vice-a-versa.

2. Parallel Communication Interface

In this type of communication, the interface gets a byte of data from the
microprocessor and sends it bit by bit to the other systems in
simultaneous (or) parallel fashion and vice-a-versa.
Types of I/O

Peripheral I/O Memory Mapped I/O

Here Peripheral is identified with an 8- Here Memory Mapped I/O is identified

bit address. with a 16-bit address.

Instructions IN and OUT are used to Data transfer is implemented by using

implement data transfer between memory related instructions, such as
Microprocessor and Peripherals. STA, STAX, LDA, LDAX, MOV etc.
Interrupts in 8085
Interrupts in 8085
An Interrupt is a process where an external device can get the attention of
the microprocessor.
 The process starts from the I/O device
 The process is asynchronous.
 An interrupt is considered to be an emergency signal that may be
serviced.
 The Microprocessor may respond to it as soon as possible.
What happens when Microprocessor is interrupted ?
 When the Microprocessor receives an interrupt signal, it suspends the
currently executing program and jumps to an Interrupt Service Routine
(ISR) to respond to the incoming interrupt.
 Each interrupt will most probably have its own ISR.
Responding to Interrupts
Interrupts in 8085
 Interrupts are the signals generated by
the external devices to request the
microprocessor to perform a task.
 There are 5 interrupt signals as follows:
1. TRAP
2. RST 7.5
3. RST 6.5
4. RST 5.5
5. INTR
Interrupts in 8085
The 8085 has 5 interrupt inputs
 The INTR input.
 The INTR input is the only non-vectored
interrupt. Interru Maskabl Vectore
 INTR is maskable using the EI/DI pt e d
instruction pair. INTR Yes No
 RST 5.5, RST 6.5, RST 7.5 are all RST 5.5 Yes Yes

automatically vectored. RST 6.5 Yes Yes

 RST 5.5, RST 6.5, and RST 7.5 are all RST 7.5 Yes Yes
maskable. TRAP No Yes
 TRAP is the only non-maskable
interrupt in the 8085
 TRAP is also automatically vectored
Classification of
Interrupts
Classification of Interrupts
 Vector interrupt:
 In this type of interrupt, the interrupt address is known to the processor.
 For example: RST7.5, RST6.5, RST5.5, TRAP.
 Non-Vector interrupt:
 In this type of interrupt, the interrupt address is not known to the processor so, the
interrupt address needs to be sent externally by the device to perform interrupts.
 For example: INTR
 Maskable interrupt:
 In this type of interrupt, we can disable the interrupt by writing some instructions
into the program.
 For example: RST7.5, RST6.5, RST5.5
 Non-Maskable interrupt:
 In this type of interrupt, we cannot disable the interrupt.
 For example: TRAP
Classification of Interrupts
 Software Interrupt:
 In this type of interrupt, the programmer has to add the instructions into the program
to execute the interrupt. There are 8 software interrupts in 8085
 For example: RST0, RST1, RST2, RST3, RST4, RST5, RST6, and RST7.
 Hardware Interrupt:
 There are 5 interrupt pins in 8085 used as hardware interrupts.
 For example: TRAP, RST7.5, RST6.5, RST5.5,INTR
Interrupt Service
Routine (ISR)
Interrupt Service Routine (ISR)
Definition
A small program or a routine that when executed, services the
corresponding interrupting source is called an ISR.
 When a device interrupts, it actually wants the Microprocessor to give a
service which is equivalent to asking the Microprocessor to call a
subroutine.
 This subroutine is called ISR (Interrupt Service Routine)
 The ‘EI’ instruction is a one byte instruction and is used to Enable the non-
maskable interrupts.
 The ‘DI’ instruction is a one byte instruction and is used to Disable the
non-maskable interrupts.
Programmable
Peripheral Interface
8255A
Programmable Peripheral Interface 8255A
 The 8255A is a general purpose programmable, parallel I/O device.
 It is designed to transfer the data from simple I/O to interrupt I/O under
certain conditions as required.
 It can be used with almost any microprocessor.
 It consists of three 8-bit bidirectional I/O ports (24 I/O lines) which can be
configured as per the requirement.
 It is flexible, versatile and economical but somewhat complex.
 The intent is to provide complete I/O interface in single chip.
 This chip directly interfaces to data bus of the processor.
8255A I/O port

PORT A 8-bit

GROUP
A

CU 4-bit
8255A CL 4-bit
PORT C I/O Devices

GROUP
B

PORT B 8-bit
8255A I/O port
8255A has three ports, i.e., PORT A, PORT B,
and PORT C.
 Port A contains 8-bit I/O latch/buffer.
 Port B is similar to PORT A.
 Port C splits into two parts, i.e. PORT C
lower (PC3-PC0) and PORT C upper (PC7-
PC4) by the control word.
 These three ports are further divided into
two groups,
 Group A includes PORT A and upper 4-bit of
PORT C.
 Group B includes PORT B and lower 4-bit of
PORT C.
These two groups can be programmed in
three different modes, i.e. the first mode is
named as mode 0, the second mode is
 Power +5V
Group Group I/O
Block diagram : 8255A
Suppliers GND A A Port A PA7-PA0
Control
Bidirectional
Data
bus Data
D0- Group
D7 Bus A Port C I/O
Buffer Upper PC7-PC4
8-bit Internal data bus

RD Group I/O
WR B Port C PC3-PC0
A1 Read Lower
Group
A0 Write B
RESET
Control Control
Logic I/O
Group
PB7-PB0
B Port B

CS
Programmable Interrupt
Controller 8259A
Programmable Interrupt Controller 8259A: Introduction

 The Intel 8259 is a Programmable Interrupt Controller (PIC) designed for

use with the 8085 and 8086 microprocessors.
 The 8085 has only five number of hardware interrupts: TRAP,RST 7.5,RST
6.5,RST 5.5 and INTR.
 The 8259 can be used for applications that use more than five numbers of
interrupts from multiple sources.
Features :8259A
The main features of 8259 are listed below
 Manage eight levels of interrupts.
 Eight interrupts are spaced at the interval of four or eight locations.
 Resolve eight levels of priority in fully nested mode, automatic rotation
mode or specific rotation mode.
 Mask each interrupt individually.
 Read the status of pending interrupt, in-service interrupt, and masked
interrupt.
 Accept either the level triggered or edge triggered interrupt.
8259 Internal Block
Diagram
59 Internal Block Diagram INTA INT

D7-D0 CONTROL LOGIC

DATA BUS
I
BUFFER
N
T
E
R
RD N
READ/WRITE A
WR IR0
LOGIC L
A0 IR1
INTERRUP IR2
IN-
CS B T IR3
SERVICE PRIORITY
U REQUEST IR4
CAS 0 CASCADE REGISTER RESOLVER
S REGISTER IR5
CAS 1 BUFFER/ (ISR)
(IRR) IR6
CAS2 COMPARATO IR7
R

SP/EN
INTERRUPT MASK REGISTER
(IMR)
Thank You