Microprocessor and Interfacing

(MPI)
GTU # 3160712

Unit-8:
Advanced
Microprocesso
r
Subject Overview

Sr. No. Unit %

Weightage
1 Introduction to Microprocessor 8%
2 Microprocessor Architecture and Operations 7%
3 8085 Microprocessor 12%
4 Assembly Language Programming Basics 13%
5 8085 Assembly Language Programs 12%
6 Stack & Subroutines 13%
7 I/O Interfacing 10%
8 Advanced Microprocessors 15%
Subject Overview

Sr. Unit Reference Books

1 Introduction to Microprocessor Microprocessor Architecture,
2 Microprocessor Architecture and Operations Programming, and Applications
with the 8085
3 8085 Microprocessor Ramesh S. Gaonkar,
4 Assembly Language Programming Basics Penram International
5 8085 Assembly Language Programs
6 Stack & Subroutines
7 I/O Interfacing
8 Advanced Microprocessors Advanced Microprocessors
Daniel Tabak, TMH

3
 Looping
Topics to be covered
 Introduction to 8086
 8086 logical block diagram
 8086 Segmentation
 8086 Pin functions
 Minimum and Maximum mode
 80286/80386:
 Overview and architecture
 Programming model,
 Data types and instruction set,
 Segments and its types
 Segment descriptor
 Descriptor table and selectors
Introduction to 8086
Introduction to 8086
 8086 is a 16-bit processor, which implies that
 16-bit data bus
 16-bit ALU
 16-bit registers
 8086 has a 20-bit address bus can access up to 220 memory locations.
( 220=1048576 bytes =1 MB)
 It can support up to 64K I/O ports. (216 I/O ports:216=65536)
 8086 has 256 vectored interrupt.
 8086 contains powerful instruction set, that also supports multiply and
divide operation.
Introduction to 8086
 8086 can operate in two modes:
i. Minimum mode: A system with only one processor i.e.8086
ii. Maximum mode: A system with multiple processors.
e.g. 8086 + math co-processor(8087),
8086+ I/O processor (8089)
 8086 uses memory segmentation. Segmentation means dividing memory
into logical components.
 In 8086 memory is divided into 16 segments of capacity 216 bytes each
and used as code, stack, data and extra segment respectively.
8086 Architecture
Block Diagram
 Memory
Interface

 6
5 Instruction

8086 Architecture
4 stream BIU
ES 3 byte
CS 2 queue
SS 1
DS
IP Control
15 0
System

15 8 7 0
AX AH AL
BX BH BL Arithmetic logic
CX CH CL unit EU
DX DH DL
SP
BP Operands
SI Flags
DI
8086 Architecture
• In 8086 CPU is divided into two independent functional units:
1.BIU (Bus Interface Unit)
2.EU (Execution Unit)
• Dividing the work between these two units speeds up the processing.
Components: BIU(Bus Interface Unit)
Instruction Queue:
It holds the instruction bytes
Address Generator: of the next instruction to be
Generates 20-bit of executed by EU(Execution
physical address. Unit).
 6
5 Instruction
4 stream BIU
ES 3 byte
CS Segment Register: 2 queue
SS 1
DS Four 16-bit register that provides
IP powerful
Instructionmemory
Pointer: management
15 0
mechanism
Register that holds 16-bit
ES (extra
address or segment), CS code
offset of next (code
segment),
byte within code segment.
SS (stack segment) , DS (data
segment).
Task of BIU

1. Fetch instructions from memory.

2. Read/write instructions to/from the memory.

3. Input/output of data to/from peripheral ports.

4. Address generation for memory reference.

5. Queuing instructions.

Thus, BIU handles all transfer of data and address.

Components: EU(Execution Unit)
EUContains 16-bit ALU,
has 4 general Performs
that
purpose 16- various internal
bitperforms add,AX,
register i.e. BX, CX,operations.
subtract, DX
increment,
each decrement,
register is the
compliment, shift,
combination AND, 8-bit
of two OR, Control
XOR etc. System
register.

15 8 7 0
AX AH AL
BX BH BL
CX CH CL
Arithmetic logic
unit
EU
DX DH DL
SP The 16-bit flagregister:
register of 8086
BP SI (Source and DI 9 active flags (6 16-bit
Operand
Index)contains
Operands
SI (DestinationFlags Index) register
are usedused by the control
DI Stackpointer:
Base pointer: used conditional
It always points
register
for to
indirect &hold
3 control
to the flags),
operands
for string
the top related
of the operation
other
stack. 7 and for
flags
Used are undefined.
addressing.
for moving block temporarily.
of memory
sequential access of stack
from one location to another.
segment.
Task of EU (Execution Unit)

1. Decodes the instruction.

2. Executes decoded instructions.

3. Tells BIU from where to fetch the instruction.

4. EU takes care of performing operation on the data.

5. EU is also known as execution heart of the processor.

 Memory
Interface

 6
5 Instruction

8086 Architecture
4 stream BIU
ES 3 byte
CS 2 queue
SS 1
DS
IP Control
15 0
System

15 8 7 0
AX AH AL
BX BH BL Arithmetic logic
CX CH CL unit EU
DX DH DL
SP
BP Operands
SI Flags
DI
Segment Register in
8086
Segment Register in 8086
1. Code Segment (CS): Stores executable program.
2. Data Segment (DS): Contains data used by a program. Data can be
accessed from this by an offset address.
3. Stack Segment (SS): Defines an area of memory used for the stack.
4. Extra Segment (ES): ES an additional data segment.
Segmentation in 8086
Segmentation in 8086
What is Segment?
An area in memory.
What is Segmentation?
The process of dividing memory into segments of various sizes is called
Segmentation.
What is need of segmentation in 8086?

What is the need of segmentation in 8086?

 Memory is huge collection of bytes.
 In order to organize these bytes in an efficient manner
segmentationis used.
E.g.No. of segments
No. of segments 16 segments

1 MB

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

64 KB
Segmentation in 8086
 Intel 8086 has 20 lines address bus.
 With 20 address lines, the memory that can be addressed is 220 bytes.
220 = 1,048,576 bytes
1 MB = 1111 1111 1111 1111 1111
= FFFFF H
Segmentation in 8086
How many segments can be accessed at a time in 8086?
 In 8086, at a time only 4 segments can be accessed.
i.e. 64 KB * 4 = 256 KB of memory can be accessed at a time.
 In 8086, memory address is ranging from 00000 H to FFFFF H.
 Bit-Size of each Segment Register is of 16-bit.
216 = 65535 bytes = 64 KB [size of each segment ]

FFFF H
SEG- 64
0000 H
1 KB

256 KB
SEG-
2
SEG-
3
Segmentation in 8086
How to calculate physical address from segment address?
 Segment Registers are used to hold the upper 16-bit of the starting
address for each of the segment.
 The 16-bit address is starting address of the segment from where the BIU
is currently fetching instruction code bytes.
 The BIU always inserts zero(0) for the LSB(Least Significant Bit) to
generate 20-bit address.
Segmentation in 8086
How a 20-bit physical address can be obtained, if data bus is of 16-
bit?
 20-bit address is known as Physical Address (PA) of memory.
 PA = Base Address : Offset
 Offset is the displacement of the memory location from the starting
location of the segment.
Segmentation in 8086
Example
Segmentation in 8086: Example

Example: Base address DS=2222 H

Step-1: Convert DS 16-bit address to 20-bit address

- the BIU appends 0 H to the LSB of the base address.

22220 H

Step-2: Retrieve offset address

- Assuming offset address = 008F H

PA = Base Address : Offset

PA = 2222 H: 008F H
Segmentation in 8086: Example
Step-3: To calculate the effective address
Physical Address = Starting Address of Segment(20-bit) + Offset
EA = 22220H
OFFSET= + 008FH
222AFH

DS 2222 H BYTE-0 22220

H
BYTE-1 22221
H
OFFSET=008F H

BYTE-N 222AF
Exercise
1. DS: Offset => 1000:1F00
8086 Flag Register
8086 Flag Register
 The 16-bit flag register of 8086 contains 9 active flags (6 conditional & 3
control flags), other 7 flags are undefined.

Flag Register (16-bit)

Control Flag Status Flag

TF: Trap Flag CF: Carry Flag
IF: Interrupt Flag PF: Parity Flag
DF: Direction Flag AF: Auxiliary Flag
ZF: Zero Flag
SF: Sign Flag
OF: Overflow Flag
8086 Flag Register

1 1 1 1 1 1
9 8 7 6 5 4 3 2 1 0
5 4 3 2 1 0
O D T S Z A P C
U U U U IF U U U
F F F F F F F F
Overflow Flag Trap Flag
Interrupt is used for single step
Flag
Direction Flag
Indicates control.
overflow,
IF=0 ; when
Disablearithmetic
Maskableoperation is
DF=0 ; String
carried bytes
out. are accessed
TF=0 from lower
; Whole program willto
behigher
Interrupt
memory
OF=0 address.
; result executed
has ;not exceeded the capacity of
IF=1 Enable Maskable
DF=1 ; String bytes
machine. are accessed
TF=1 ; Programfrom higher
will run to lower
in single
Interrupt
memory
OF=1 address.
; result step mode.
has exceeded the capacity of
machine.
8086 Flag Register
 Carry Flag (CF): Set(1) if arithmetic operation results in carry; otherwise
reset(0).
 Auxiliary Flag (AF): If an operation performed in ALU generates a
carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7),
the AF flag is set i.e. carry given by D3 bit to D4 is AF flag. This is not a
general-purpose flag, it is used internally by the processor to perform
Binary to BCD conversion.
 Parity Flag (PF): This flag is used to indicate the parity of result. If lower
order 8-bits of the result contains even number of 1’s, the Parity Flag is set
and for odd number of 1’s, the Parity Flag is reset.
 Zero Flag (ZF): It is set(1), if the result of arithmetic or logical operation
is zero else it is reset(0).
 Sign Flag (SF): In sign magnitude format the sign of number is indicated
by MSB bit. If the result of operation is negative, sign flag is set(1).
 8 08 6
p in d
iagram

8086 pin diagram

 Maximum ModeMinimum Mode
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3
AD12 4 37 A17/S4

8086 Pin Diagram AD11 5 36 A18/S5

AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
RQ/GT0
AD6 10 31
(HOLD)
8086
RQ/GT1
AD5 11 30
(HLDA)
AD4 12 29 LOCK (WR)
AD3 13 28 S2 (M/IO)
AD2 14 27 S1 (DT/ R)
AD1 15 26 S0 (DEN)
AD0 16 25 QS0 (ALE)
NMI 17 24 QS1 (INTA)
INTR 18 23 TEST
Address and Data pins: AD0-AD15 (bidirectional)
 These lines are multiplexed bidirectional
address/data bus.
 AD0-AD7 carry lower order byte of data and
AD8-AD15 carry higher order byte of data.
 When ALE=1, then Address bus gets
enabled, else Data bus will get enabled.
Address and Status pins:A16/S3- A19/S6
 Lines are multiplexed and unidirectional
address with status bus.
 During T1, they carry higher order
address.
 In the remaining clock cycles, they carry
status signals.
 S5 gives the status of Interrupt Flag (IF)
 S6 goes low, when 8086 controls the
shared system bus.
 S3 and S4 indicates the segment register.
Status pins
 Below table indicates, which segment will
be accessed on the basis of S4 & S3 bit
value.
S4 S3 Register
0 0 ES

0 1 SS

1 0 CS

1 1 DS
BHE/S7
 BHE stands for Bus High Enable is active low
output signal.
 BHE signal is used to indicate the transfer of
data over higher order data bus (D8- D15).
 8-bit I/O devices use this signal.
 S7 is reserved for future development.
Interrupt Pins
 NMI
 It is an active high input signal.
 It is a non-maskable interrupt signal.
 INTR
 It is an active high input signal
 It is an interrupt request signal.
 INTA
 It is an active low output signal.
 This is an interrupt acknowledge signal.
Clock Pin: CLK
 Generates clock signals that synchronizes
the operation of processor.
 8086 clock frequency: 5MHz-10MHz
Clock Pin: RESET
 Active high input signal.
 When high, microprocessor enters
into reset state and terminates all the
activities of processor.
 Processor requires 4 clock cycles to
reset.
 Thus, RESET signal must be 1 for at
least 4 clock cycles.
Clock Pin: READY
 Active high input signal.
 This is an acknowledgement signal from
I/O devices or memory.
 When high, it indicates that device is
ready to transfer data.
 When low, microprocessor is in wait state.
Control Pin: Test
 Active low input signal.
 It is used to test the status of math
coprocessor 8087.
 The BUSY pin of 8087 is connected to this
pin of 8086.
 If low, execution continues, else
microprocessor is in idle state.
Control Pin: MN/MX
 8086 works in two modes:
1. Minimum Mode (Active high i/p signal)
2. Maximum Mode (Active low i/p signal)
• Pins from 24 to 31 issue two different sets of
signals.
• One set of signals is issued when CPU operates
in minimum mode, while other is issued when
CPU operates in maximum mode.
Mode Multiplexed pins: S2, S1, S0

S2 S1 S0 Indication
0 0 0 Interrupt
0 0 1 Read I/O
acknowledgement
0 1 0 Write I/O
0 1 1 HALT
1 0 0 Code Access
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive
Mode Multiplexed pins
 DEN
 Active low output signal.
 This is a Data Enable signal, which is used to
enable the transceiver.

 DT/R
 Data Transmit/Receive signal.
 When high, data is transmitted out else when
low, data is received in.
Mode Multiplexed pins: M/IO
 This signal is issued by the microprocessor
to distinguish memory access from I/O
access.
 When high, memory is accessed, else when
low, I/O devices are accessed.
Mode Multiplexed pins: QS1 and QS0

QS QS
Indication
1 0 0 0 No operation
First byte of opcode from
0 1
1 0 queue
Empty the queue
Subsequent byte from
1 1
queue
Mode Multiplexed pins
LOCK
 Active low output signal.
 This signal indicates that other processors
should not ask CPU (8086) to hand over
the system bus.
 This pin is activated by using LOCK prefix
to any instruction.

WR
 Active low output signal.
 Used to write data in memory or output
signal, depending on status of M/IO signal.
Mode Multiplexed pins
HOLD
 Active high input signal.
 When DMA controller needs to use
address/data bus, it sends a request to the
CPU through this pin.
 When microprocessor receives HOLD signal,
it issues HLDA signal to the DMA controller.

HLDA
 Active high Hold Acknowledgement output
signal.
 It is issued by 8086 after receiving HOLD
signal.
Mode Multiplexed pins
RQ/GT0 and RQ/GT1
 Request/Grant bi-directional pins.
 Other processors request the CPU(8086)
through these lines to release the system
bus.
 After receiving the request, CPU sends
acknowledge signal through the same lines.
 RQ/GT0 has higher priority than RQ/GT1.
 Maximum ModeMinimum Mode
GND 1 40 VCC
AD14 2 39 AD15
AD13 3 38 A16/S3
AD12 4 37 A17/S4

8086 Pin Diagram AD11 5 36 A18/S5

AD10 6 35 A19/S6
AD9 7 34 BHE/S7
AD8 8 33 MN/MX
AD7 9 32 RD
RQ/GT0
AD6 10 31
(HOLD)
8086
RQ/GT1
AD5 11 30
(HLDA)
AD4 12 29 LOCK (WR)
AD3 13 28 S2 (M/IO)
AD2 14 27 S1 (DT/ R)
AD1 15 26 S0 (DEN)
AD0 16 25 QS0 (ALE)
NMI 17 24 QS1 (INTA)
INTR 18 23 TEST
80286
80286
 The Intel 80286 had a 24-bit address bus and was able to
address up to 16 MB of RAM compared to 1 MB of its
predecessor (8086).
 It was designed for multi-user systems with multitasking
applications, including communications and real-time
process control.
 80286 is the advanced microprocessors with memory
management and protection abilities.
 80286 have two operating modes namely real address
mode and virtual address mode.
 In real address mode, it can address up to 1MB of
physical memory address like 8086.
 In virtual address mode, it can address up to 16 MB of
physical memory address space and 1 GB of virtual
memory address space.

80286 Architecture
ADDRESS UNIT BUS UNIT 80286 Architectur
A0-A23 80286 contains 4
ADDRESS BHE
PHYSICAL M/IO separate
LATCHES AND DRIVERS
ADDRESS processing units
ADDER
PROCESSOR PEACK
1. Bus Unit (BU)
SEGMENT PREFETCHER EXTENSION PEREQ
BASES INTERFACE
2. Instruction Unit
READY,
SEGMENT HOLD (IU)
LIMIT SEGMENT BUS CONTROL 3. Address Unit
CHECKER SIZE S1,S0,
OFFSET (AU)
ADDER DATA TRANSCEIVERS COD/INTA 4. Execution Unit
D15-D0
LOCK,HLD
A (EU)
6-BYTE
PREFETCH
QUEUE

ALU
RESET
REGIS
control 3 CLK
TERS INSTRUCTI
DECODED VSS
ON
INSTRUCTI VCC
DECODER
ON QUEUE
ERROR

CAP
EXECUTION UNIT INSTRUCTION UNIT
BUSY
INTR
NMI
80286 Architecture: Bus Unit (BU)
Components:
1. Address Latches & Drivers
2. Bus Control
3. Instruction Pre-fetcher
4. Processor Extension Interface
5. Data Transceivers
6. 6-byte Instruction Queue
80286 Architecture: Bus Unit (BU)
Functions:
 Perform all memory, I/O read and write
operations.
 Pre-fetch the instruction bytes.
 To control transfer of data to and from
processor extension devices like
80287 math co-processor.
 Whenever BU is not using the buses, it
pre-fetches the instruction bytes and
put them in 6 byte pre-fetch queue.
 Take care of communication between
CPU and a Co-processor.
80286 Architecture: Instruction Unit (IU)
Components:
1. 3 decoded instruction queue
2. Instruction decoder
Functions :
 It fully decodes up to 3 pre-fetched
instructions and holds them in a queue, so
that Execution Unit (EU) can access them.
 It helps processor to speed up by pipelining
the instructions.
80286 Architecture: Execution Unit (EU)
Components:
 It includes ALU, registers and control unit.
 Registers are general purpose, index, pointer, flag
registers and Machine Status Word (MSW).
Functions:
 To sequentially execute instructions received from
the instruction unit.
 ALU result is either stored in registers or sent back
over data bus.
80286 Architecture: Address Unit
Components:
1. Segment Bases
2. Segment Limit Checker
3. Segment Size
4. Offset address
5. Physical address adder
Functions:
 It computes physical address
that will be sent out to the memory
or I/O by Bus Unit (BU).
 80286 operate in two different modes
1. Real address mode
2. Protected Virtual Address Mode.
ADDRESS UNIT BUS UNIT 80286 Architectur
A0-A23 80286 contains 4
ADDRESS BHE
PHYSICAL M/IO separate
LATCHES AND DRIVERS
ADDRESS processing units
ADDER
PROCESSOR PEACK
1. Bus Unit (BU)
SEGMENT PREFETCHER EXTENSION PEREQ
BASES INTERFACE
2. Instruction Unit
READY,
SEGMENT HOLD (IU)
LIMIT SEGMENT BUS CONTROL 3. Address Unit
CHECKER SIZE S1,S0,
OFFSET (AU)
ADDER DATA TRANSCEIVERS COD/INTA 4. Execution Unit
D15-D0
LOCK,HLD
A (EU)
6-BYTE
PREFETCH
QUEUE

ALU
RESET
REGIS
control 3 CLK
TERS INSTRUCTI
DECODED VSS
ON
INSTRUCTI VCC
DECODER
ON QUEUE
ERROR

CAP
EXECUTION UNIT INSTRUCTION UNIT
BUSY
INTR
NMI
Register Organization
of 80286
Register Organization of 80286
 Eight 16-bit general purpose
registers (AX, BX, CX, DX, SP, BP, SI,
DI).
 Four 16-bit segment registers (CS,
SS, DS, ES).
 16-bit Instruction Pointer (IP).
 16-bit Flag Register.
 Additionally, one new 16-bit
Machine Status Word (MSW)
register. Flag Register

MSW
80286 Flag Register
80286 Flag Register

1 1 1 1 1 1
5 4 3 2 1
9 8 7 6 5 4 3 2 1 0
0
N O D T S Z A P C
U IOPL IF U U U
T F F F F F F F F

Nested Task (NT) flag

Input Output Privilege Level flag (IOPL)
• It is used in protected mode.
• Used in protected mode operation to select the
• Bit is set when one task invokes
privilege level for I/O devices.
another task.
• 00, 01, 10 and 11 are various bits of privilege
level; 00 is the highest and 11 is the lowest
privilege level respectively.
80286 Flag Register: Machine Status Word (MSW)

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6
E M
TS PE
M P

TaskEMulate processor
Monitor
Switch extension
Processor flag
extension
TS isIfautomatically
SET,IfEMulate
SET,
Used this
to
coprocessor
flag
SET allows
whenever
indicate
bit
a is ainstruction
WAIT
whether
set to
processor
cause all coprocessor
task switchtooperation
generateisa opcodes to
processor extension
performed. notin
generate extension
a Protected(co-processor)
Coprocessor is
Not Availablepresent
present
the exception.
system or Mode
not. Enable
fault. PE=1; Places 80286 in protected
mode
PE=0; It can be only RESET by
resetting CPU
Real Address Mode
80286
80286: Real Address Mode
Real Mode
 Address Unit computes the address with segment base and offset like
8086.
 Maximum physical space allowed in this mode is 1MB.
 When 80286 get RESET, it always starts execution in real mode.
Task of 80286 in Real Mode
 Initializes Instruction Pointer(IP) and other registers of 80286.
 Initializes the peripheral.
 Enable Interrupts.
 Set up descriptor table.
 Prepares for entering in PVAM (Protected Virtual Address Mode).
Physical Address calculation in Real Address
Mode
Address Calculation 15 0
000 OFFSET
 Total 1MB of Memory, divided among 16- 0
OFFSET
ADDRESS
segments with each of size 64kb.
 80286 reserves two fixed areas for 15 0
i. System Initialization SEGMENT 000 SEGMENT
SELECTION 0 ADDRESS
ii. IVT (Interrupt Vector Table)

IVT-1KB of Starting 00000H –

ADDER
address 003FFH
System FFFF0H – FFFFFH
Initialization
20-BIT PHYSICAL
MEMORY ADDRESS
Physical Address calculation in Real Address
Mode

Physical Address = Starting Address of Segment(20-bit) + Offset

EA = 22220H
OFFSET= + 008FH
222AFH

DS 2222 H BYTE-0 22220

H
BYTE-1 22221
H
OFFSET=008F H

BYTE-N 222AF
Protected Virtual
Address Mode
80286
What is the role of MMU?
 Memory Management Unit (MMU) translates the virtual memory address
into the physical memory address.
 Virtual memory can be many times larger than physical memory.
 Only programs that are currently required brought from the secondary
storage such as a hard disk to the physical memory (RAM) for execution.
 This is desirable as a microprocessor is supposed to store large programs
and data can’t be accommodated in the physical memory space.
What is the role of MMU?
 The hard disk is in the virtual or logical address space but not in the
physical address space.
 Faster memory such as RAM is used as the physical memory.
 Before microprocessor executes a program, it checks whether the program
is available in physical memory (RAM) or not.
 If program is not available in the physical memory, it is brought from the
secondary memory to the physical memory.
 If available space is inadequate in the physical memory, some less
important/unused program can be swapped back to the secondary
memory to create space.
80286: Protected Virtual Address Mode
 286 is the 1st processor to support the concept of Virtual Memory and
Memory Management.
 Here, the address unit acts as Memory Management Unit (MMU).
 All 24 address lines are used and can access up to 16MB of physical
memory.
 If descriptor table scheme is used it can address up to 1GB of virtual
memory.
 The complete virtual memory is mapped with the 16MB of physical
memory.
 If a program is larger than 16MB, it is stored in the hard disk and will be
executed by swapping as per sequence of execution.
 The huge programs are divided in smaller segments or pages arranged in
appropriate sequence.
Physical Address calculation in PVAM
PHYSICAL MEMORY

CPU
POINTER

SELECTOR OFFSET

SEGMENT
MEMORY
OPERAND
PHYSICAL
ADDRESS
ADDER
SEGMENT
SEGMENT DESCRIPTOR
DESCRIPTO TABLE
SEGMENT R
24-bit
BASE
ADDRESS
Real mode vs PVAM

Real Address Mode Protected Virtual Address

Mode
Can only address up to 1MB of system Can address up to 16MB of System
memory
Doesn’t and act asthe
Support fastconcept
8086. of Virtual Memory.
Supports the concept of Virtual Memory.
Memory.
Real mode provides no support for Protected mode provides support for
memory protection, multitasking, or code memory protection, multitasking, or code
privilege levels.
Initially every processor is in Real Mode i.e privilege levels. will switch to PVAM mode
Microprocessor
MSW PE-bit to 0. by setting MSW PE-bit to 1.
80286 Privilege Level
80286 Privilege Level
11
Applications
(Lowest
Privilege 01
Level) OS
Service

00
Kernel
Level
(highes
t)

10
OS
Extensi
on
PVAM : Selector
PVAM : Selector
TI-Table Indicator
TI=0 : GDT(Global Descriptor
Table)
TI=1 : LDT(Local Descriptor
Table)
1 1 1 1 1 1
5 4 3 2 1
9 8 7 6 5 4 3 2 1 0
0
T
Selector RPL
I

Bit 3-15 points to 00 Kernel Level

the Entry of 01 OS Services
Descriptor Table 10 OS Extension
11 Application
Level
Segment Descriptor:
PVAM Descriptor
80286
 Segment Descriptor: PVAM Descriptor
 This smaller segments or pages have been associated with data structure
called a Descriptor.
 It contains information of program segment or pages.
 The data structure Descriptor is essentially one such identifier of
particular program or segment.
 The set of such descriptor arranged in a proper sequence describes the
complete program.
pes of Segment Descriptor
Data Segment Descriptor Used for Data Segment
Code Segment Descriptor Used for Code Segment
System Segment Used for System
Descriptor
Gate Segment Descriptor Programs
Used for Subroutine and
ISR
Descriptor Table
GDT & LDT
What is Descriptor Table?
Definition
 The descriptor is a block of contiguous memory location containing
information of a segment, like
i. Segment base address
ii. Segment limit
iii. Segment type
iv. Privilege level – prevents unauthorized access
v. Segment availability in physical memory
vi. Descriptor type
vii. Segment use by another task
Descriptor Table: GDT & LDT
 A segment cannot be accessed, if its descriptor does not exist in either
LDT (Local Descriptor Table) or GDT (Global Descriptor Table).
 Set of descriptor arranged in a proper sequence describes the complete
program.
 Each Descriptor is 8-byte long.
Descriptor Table: GDT & LDT
 The GDT contains information about segments that are global in nature,
that is, available to all programs and normally used most heavily by the
operating system.
 The LDT contains descriptors that are application specific.
 A global descriptor is also known as System Descriptor, and local
descriptor is know as Application Descriptor.
 The global descriptor table’s base address is stored in GDTR.
 The local descriptor table’s base address is stored in LDTR.
Descriptor Table: GDT & LDT
Differentiate GDT and
LDT
Differentiate GDT and LDT
 LDT (Local Descriptor Table), acts similar to
GDT, which also saves segments descriptor.
 The main differences between GDT and LDT is:
1. GDT have only one copy in system while
LDT can have many.
2. GDT may not changed during execution,
while LDT often changes when task
switches.
3. Entry of LDT is saved in GDT.
4. Entries in GDT and LDT have the same
structure.
Data/Code Segment
Descriptor
Data/Code Segment Descriptor

15 8 7 0

7 INTEL RESERVED 8

5 P DPL S TYPE A BASE 23-16

6

3 BASE 15-0 4

1 LIMIT 15-0 2
Data/Code Segment Descriptor

7 6 5 4 3 2 1 0
P DPL S E ED/ R/W A
C

Read : Code
Expansion Segment
Direction: Executable
Data Segment {when E=0}
R=0 Code Segment execute Accessed
only,
E=0: DataTYPE
Segment
ED=0 Segment expands upward (Data segment)
not
ED=1
Sets readable
theSegment expands
Descriptor downward
Privilege Level A=0
E=1: Segment
Code
(Stack
(DPL) not
Segment
Segment)
necessary accessed
for
P=0: Descriptor is undefined, noA=1 mapping to
Segment has been accessed
R=1
protection Code Segment both
physical memory exists.
executable & readable
P=1: Segment is mapped
S=0:Conforming:
System into Segment
Code physical {when E=1}
descriptor(GDT)
memory.S=1:C=0 Ignore DPL
Application Descriptor(LDT)
Write : Data Segment
C=1 Code segment will only be executed when
W=0 Data segment not writable
CPL > DPL
W=1 Data segment writable
80386
80386: Introduction
 80386 is 32-bit microprocessor.
 Address Bus: 32-bit
 Data Bus: 32-bit
 Physical memory : 4GB
 Virtual memory : 64TB
 80386 supports variety of operating clock frequency, which are 16 MHz,
20 MHz, 25 MHz and 33 MHz.
 80386 supports 3 operating modes: real, protected and virtual real mode.
 Key characteristics: Multitasking and protection capability.
 80386 has an internal dedicated hardware that permits multitasking.
 3 stage pipeline: fetch, decode and execute.
 it supports simultaneous fetching, decoding and execution inside the system.
80386 Architecture
80386 Architecture
Execution Unit Segment Unit Paging Unit

Segment Page
Register File Descriptor Descriptor
Barrel Shifter Cache Cache
ALU Segment
Page Unit
Unit

Instruction Pre- Pre-

Queue fetch fetch BUS UNIT
Queue Unit
Instruction Unit

Instruction Decoder Unit Code Pre-fetch Unit Bus Interface Unit

Bus Interface Unit
 The Bus Interface Unit connects 80386 with memory
and I/O.
 Based on internal requests for fetching instructions and BUS UNIT
transferring data from the code pre-fetch unit, 80386
generates the address, data and control signals for the
current bus cycles.
Bus Interface Unit
Code Pre-fetch Unit
 The code pre-fetch unit pre-fetches instructions when the
bus interface unit is not executing the bus cycles. Pre- Pre-
fetch fetch
 It then stores them in a 16-byte instruction queue for
Queue Unit
decoding by the instruction decode unit.
Code Pre-fetch Unit
Instruction Decoder Unit
 The Instruction Decoder Unit translates instructions
Instruction
from the pre-fetch queue into micro-codes.
Queue
 The decoded instructions are then stored in an
instruction queue (FIFO) for processing by the execution Instruction Unit
unit.
Instruction Decoder Unit
Execution unit
 Execution unit has 8 General purpose registers which Execution Unit
are either used for handling data or calculating offset
addresses. Register File
 The execution unit processes the instructions from the Barrel Shifter
instruction queue. ALU
 It contains a control unit, a data unit and a protection
test unit.
 The barrel shifter increases the speed of all shift and
rotate operations.
Segment Unit
 The segment unit calculates and translates the logical Segment Unit
address into linear addresses at the request of the Segment
execution unit. Descriptor
Cache
Segment
Unit
Paging Unit
 The translated linear address is sent to the Paging Unit. Paging Unit

 Upon enabling the paging mechanism, the 80386 Page

Descriptor
translates these linear addresses into physical addresses. Cache
 If paging is not enabled, the physical address is identical
Page Unit
to the linear address and no translation is required.
80386 Architecture
Execution Unit Segment Unit Paging Unit

Segment Page
Register File Descriptor Descriptor
Barrel Shifter Cache Cache
ALU Segment
Page Unit
Unit

Instruction Pre- Pre-

Queue fetch fetch BUS UNIT
Queue Unit
Instruction Unit

Instruction Decoder Unit Code Pre-fetch Unit Bus Interface Unit

80386 Register
Organization
80386 Register Organization
31 0 SEGMENT REGISTER
EA AX ACCUMULATOR CS
X SS
BASE INDEX
EB BX
COUNT DS
X
DATA ES Data
EC CX
X STACK POINTER FS Segment
ED DX BASE POINTER GS
X SOURCE INDEX 15 0
ES SP DESTINITION INDEX
P
EB BP
P 31 0
ESI EIP SI IP
ED EFLA DI FLAGS
I GS
80386 Register Organization: Flag Register

1 1 1 1 1 1
5 4 3 2 1
9 8 7 6 5 4 3 2 1 0
0
N O D T S Z A P C
U IOPL IF U U U
T F F F F F F F F

3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6
R
VM
F
Resume Flag
• It is used in conjunction with the debug register breakpoints.
Virtual Mode Enable
• When RF is set(1), it causes any debug fault to be ignored on the
When VM=1; 386 will switch from Protected to
next instruction.
virtual mode
• The RF flag temporarily disables debug exceptions so that an
instruction can be restarted.
• RF is then automatically reset at the successful completion of
Operating Modes of 80386
1. Real Address Mode
2. Protected Virtual Address Mode
3. Virtual Mode
80386: Real Address Mode
 When 80386 resets, the initial operating mode is Real Address Mode.
 In real address mode, 80386 works as a fast 8086 with 32-bit registers
and data types.
 Real-address mode is in effect after a signal on the RESET pin.
 Even if the system is going to be used in protected mode, the start-up
program will execute in real mode temporarily while initializing for
protected mode.
 The addressing techniques, memory size, interrupt handling in this mode
of 80386 are similar to the real addressing mode of 80286.
 In real address mode, the default operand size is 16-bit but 32-bit
operands and addressing modes may be used with the help of override
prefixed instructions.
 Maximum physical memory = 1MB.
80386 :PVAM
 MMU operates similar to 80286.
 Virtual addresses are represented with a selector component and an offset
component.
 The selector component is used to index a descriptor in a descriptor table.
 The descriptor contains the 32-bit physical base address for the segment.
 The offset part of the virtual address is added to the base address to
produce the actual physical address.
 The offset part of a virtual address can be 16-bit or 32-bit, so segment can
be as large as 4GB.
 Hence the virtual memory size is 64TB.
Operating Modes of 80386 :PVAM
 Advantage of segmentation of memory: Segments corresponds to
code and data structures in the program. Hence segmentation is useful.

 Limitation of segmentation of memory: If we need only a part of

memory, even then we have to swap the whole segment content. This will
increase the time for execution.
80386:Virtual Mode
Virtual Mode (Paged Mode)
 In virtual mode, 8086 can address 1MB of physical memory that may be
anywhere in the 4Gbytes address space of the protected mode of 80386.
 In this mode, instead of segments, 4KB of fixed page length are used.
80386:Virtual Mode

Total memory available for paging = 1MB = 1024KB

Size of one page = 4KB

How many pages can be addressable with 1MB of memory?

Total pages= 1024KB/4KB = 256 pages(4KB each)

Paged Mode
 Limitation : Pages do not correspond to the logical structure of the
program.

 Advantage : Pages can be quickly swapped.

80386 Memory Access
in
Virtual Mode
80386 Memory Access in Virtual Mode

Selector
Segmentatio
Linear Address Paging Physical Address
Offset n
Mechanism
Mechanism
Operating Modes of 80386:VM
Page Directory Entry
Each directory entry is of 4 byte
31 12 11 10 9 8 7 6 5 4 3 2 1 0
Page Table Address U R
Reserv
0 0 D A 0 0 / / P
(A31-A12) ed
S W

D: Dirty bit
P: A Present
:Accessed bitare
bit is set by 80386 before
The upper 20-bit
Dirty (A
U/31
bit is-Aset
21) before
R/ Permitted
any Permitted
write operation forany
• access
P=0,
S to W indicates
the page entry
for Level 3 cannot
Level 2,1beor used
0 for
used to select
to the 1024
page. page
table entries. Aaddress
= 0,
Page
translation.
page is not accessed.
Dirty 0Tables
bit are can
0undefined
None for page directory
Read/Write
• AP=1,
= 1, indicates
page is entry can be used for address
accessed.
be shared between
entries.0the 1task.
translation. None Read/Write
P-bit of currently executed page
is always
1 0high.
Read-only Read/Write
1 1 Read-Write Read/Write
Operating Modes of 80386:VM
 Page Table Entry
Each page table is of 4KB in size and contain maximum 1024 pages.

31 12 11 10 9 8 7 6 5 4 3 2 1 0
Page Frame Address U R
Reserv
0 0 D A 0 0 / / P
(A31-A12) ed
S W

D: Dirty bit
P:A Present
The upper 20-bitDirty
(A :Accessed
31-A12)isare
bitbit is set by 80386 before any
U/
bit R/ before
set Permitted Permitted
any write operation for
•
used to select to1024 P=0,
access to W
Spage indicates
the page entry
for Level 3 cannot
Level 2,1 beor used
0 for
the page.
Aaddress
entries. Page Tables =can
0, pagetranslation.
be is not accessed.
Dirty
• bit
0 are 0undefined
None for page directory
Read/Write
shared between the A P=1,
= 1,
task. indicates
page is entry
accessed.can be used for address
entries. 0 1 None Read/Write
translation. P-bit of currently executed page is
always1 high.
0 Read-only Read/Write
1 1 Read-Write Read/Write
Page Translation
Mechanism in 80386
Page Translation Mechanism in 80386
Format of Linear Address
A linear address refers indirectly to a physical address by specifying a page
table, a page within that table, and an offset for that page.

31 22 21 12 11 0
DIRECTORY TABLE OFFSET
Linear Address
31 22 21 12 11 0
DIRECTORY TABLE OFFSET

USER MEMORY

80386
+ Memory
31PAGE TABLE0

31DIRECTORY0 +

CONTROL +
REGISTERS
CR3
80386:Page Translation Mechanism
80386:Page Translation Mechanism
CR3: Enables processor to translate linear addresses into physical
addresses by locating the page directory and page tables for the
current task.
 Here processor converts the DIRECTORY, TABLE, and OFFSET fields of a
linear address into the physical address by consulting two levels.
Comparison of different
Intel Processors
Comparison of different Intel Processors
Parameter 8085 8086 8028 803 804 Penti
N-bit Processor 8-bit 6
16- 16-bit 86
32- 86
32- um
64-bit
(data bus)
Address bus 16- bit
20- 24-bit bit
32- bit
32- 32-bit
Addressable bit
64KB bit
1MB 16MB bit
4GB bit
4GB 4GB
Memory
Introduced in Year 1976 1978 1982 1985 1989 1993
Support Virtual NO NO YES YES YES YES
Memory
Support NO YES YES YES YES YES
Segmentation
Supports Paging NO NO NO YES YES YES
Operating Modes 1 2 3 3 3 3
Support Cache NO NO NO NO YES YES
Memory
Contains on-chip NO NO NO NO YES YES
FPU
Supports Instruction NO YES YES YES YES YES
Queue
References

Books: Advanced Microprocessors, Daniel Tabak, McGrawHill

8086 Programming and Advance Processor Architecture, Savaliya

M. T., WileyIndia

The 8088 and 8086 Microprocessors, Triebel & Singh, Pearson

Education

Mobile 8085 and 8086 Microprocessor Opcodes app from Play Store:

Application: http://tiny.cc/aopcodes
Thank You