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PCIe Presentation

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Sachin R Devang
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PCIe Presentation

Uploaded by

Sachin R Devang
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© © All Rights Reserved
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PCIe G4

IP Verification
Sachin K R
Date: 11th-Nov-2022
Agenda

. Introduction
. History
. Overview Of PCIeG4
. Block Diagram
. Features
. Use Cases
. References
INTRODUCTION
What is PCIe?

PCIe stands for Peripheral Component Interconnect express.

It is high-speed serial computer expansion bus standard designed to replace the older
PCI,PCI-X bus standards.
History

Throughput
PCI Express Line Transfer
Introduced
version code rate
×1 ×2 ×4 ×8 ×16

1.0 2003 8b/10b 2.5 GT/s 250 MB/s 0.50 GB/s 1.0 GB/s 2.0 GB/s 4.0 GB/s

2.0 2007 8b/10b 5.0 GT/s 500 MB/s 1.0 GB/s 2.0 GB/s 4.0 GB/s 8.0 GB/s

3.0 2010 128b/130b 8.0 GT/s 984.6 MB/s 1.97 GB/s 3.94 GB/s 7.88 GB/s 15.8 GB/s

4.0 2017 128b/130b 16.0 GT/s 1969 MB/s 3.94 GB/s 7.88 GB/s 15.75 GB/s 31.5 GB/s

5.0 2019 128b/130b 32.0 GT/s 3938 MB/s 7.88 GB/s 15.75 GB/s 31.51 GB/s 63.0 GB/s

PCI Express Link Performance – from Wikipedia


Overview Of PCIeG4
The F-Tile Intel Quartus Prime Hard IP supports PCI Express Gen4 in Endpoint, Root
Port and TLP Bypass Modes.

The F-Tile Intel Quartus Prime Hard IP supports Avalon Streaming user interfaces.

F-tile serves as a companion tile for Intel Agile devices.

F-tile PCIe QHIP IP consists of the following major sub-blocks:


PMA/PCS (F-Tile General Purpose Transceiver (FGT))
Four PCIe cores (1 x16 capable core, 1 x8 capable core and 2 x4 capable cores),
EMIB
Soft Logic blocks
Block Diagram
Phy Channel Assignement per Bifurcation mode
Bifurcation Mode Port 0 (x16) Port 1 (x8) Port 2 (x4) Port 3 (x4)

1 x16 0 - 15 NA NA NA

2 x8 0–7 8 - 15 NA NA

4 x4 0-3 8 - 11 4-7 12 - 15
Available Topo and correspond Common Switch

Note: Refer to qhip_cs.arf on what


define will be set if the cs was called
Configuration Modes Supported by the F-tile Avalon-ST IP for
PCI Express:

The four cores in the PCIe Hard IP can be configured to support the following topologies :-
PCIe G4 Features

- Complete protocol stack including the Application, Transaction, Data Link and Physical Layers
implemented as a Hard IP.

- Supports up to 512-byte maximum payload size (MPS).

- Supports Single Virtual Channel (VC).


- Supports D0 and D3 PCIe power states.
- Supports Virtualization.
- Alternative Routing-ID Interpretation (ARI).
- Function Level Reset (FLR).
- Variable PLD clock frequencies: (350 MHz / 400 MHz / 450 MHz / 500 MHz for Intel Agilex)
Use Cases
PCIe Gen4x16 Endpoint with Xeon server interconnect for Accelerator applications. Including
Virtualization support (SRIOV, SIOV and VIRTIO).

PCIe Gen4x16 Root Port for FPGA-SOC (ARM) hosted PCIe systems.

PCIe Gen4 2x8 or 1x8 Endpoint with SRIOV for FPGA Virtualization data center applications.

PCIe Gen4 4x4 Root ports for FPGA-hosted NVMe SSD storage applications.
References :
1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide
2. F-Tile PCIe QHIP HIGH-LEVEL ARCHITECTURE SPECIFICATION
3. PCI Express Base Specification Revision 5.0 Version 0.9
4. https://wiki.ith.intel.com/display/PSGPIPEVPG/GDR+PCIe+QHIP
THANK YOU
About Capgemini
Capgemini is a global leader in partnering with companies to transform and
manage their business by harnessing the power of technology. The Group is
guided everyday by its purpose of unleashing human energy through
technology for an inclusive and sustainable future. It is a responsible and
diverse organization of 270,000 team members in nearly 50 countries. With its
strong 50 year heritage and deep industry expertise, Capgemini is trusted by its
clients to address the entire breadth of their business needs, from strategy and
design to operations, fuelled by the fast evolving and innovative world of cloud,
data, AI, connectivity, software, digital engineering and platforms. The Group
reported in 2020 global revenues of €16 billion.

Get the Future You Want | www.capgemini.com

This presentation contains information that may be privileged or confidential


and is the property of the Capgemini Group.
Copyright © 2021 Capgemini. All rights reserved.

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