Lecture 9:

Combinational
Circuit Design
 Outline
 Bubble Pushing
 Compound Gates
 Logical Effort Example
 Input Ordering
 Asymmetric Gates
 Skewed Gates
 Best P/N ratio

10: Combinational Circuits CMOS VLSI Design 4th Ed. 2

 Example 1
module mux(input s, d0, d1,
output y);

assign y = s ? d1 : d0;
endmodule

1) Sketch a design using AND, OR, and NOT gates.

D0
S
Y
D1
S

10: Combinational Circuits CMOS VLSI Design 4th Ed. 3

 Example 2
2) Sketch a design using NAND, NOR, and NOT gates.
Assume ~S is available.

D0
S
Y
D1
S

10: Combinational Circuits CMOS VLSI Design 4th Ed. 4

 Bubble Pushing
 Start with network of AND / OR gates
 Convert to NAND / NOR + inverters
 Push bubbles around to simplify logic
– Remember DeMorgan’s Law

Y Y

(a) (b)

Y Y

D
(c) (d)

10: Combinational Circuits CMOS VLSI Design 4th Ed. 5

 Example 3
3) Sketch a design using one compound gate and one
NOT gate. Assume ~S is available.

D0
S
Y
D1
S

10: Combinational Circuits CMOS VLSI Design 4th Ed. 6

 Compound Gates
 Logical Effort of compound gates
unit inverter AOI21 AOI22 Complex AOI

Y A Y  AB  C Y  AB  C D Y  AB  C   D E

D
A A E
Y
B B A
A Y Y Y
C C B
D C

A 4 B 4 A 4 B 4 B 6
2 C 4 C 4 D 4 C 6 A 3
A Y Y Y
1 A 2 A 2 C 2 D 6 E 6
C 1 Y
B 2 B 2 D 2 E 2 A 2
D 2 B 2 C 2

gA = 3/3 gA = 6/3 gA = 6/3 gA = 5/3

p = 3/3 gB = 6/3 gB = 6/3 gB = 8/3
gC = 5/3 gC = 6/3 gC = 8/3
p = 7/3 gD = 6/3 gD = 8/3
p = 12/3 gE = 8/3
p = 16/3

10: Combinational Circuits CMOS VLSI Design 4th Ed. 7

 Example 4
 The multiplexer has a maximum input capacitance of
16 units on each input. It must drive a load of 160
units. Estimate the delay of the two designs.
H = 160 / 16 = 10 B = 1 N = 2
D0 D0
S S
Y Y
D1
D1
S S

10: Combinational Circuits CMOS VLSI Design 4th Ed. 8

 Example 5
 Annotate your designs with transistor sizes that
achieve this delay.

8 8
8 10 10
8 25 25 10 10 24
Y Y
25 6 6 12
8 8 25 6 6
8
8
16 160 * (4/3) / 4.2 = 50 16 160 * 1 / 4.5 = 36

10: Combinational Circuits CMOS VLSI Design 4th Ed. 9

 Input Order
 Our parasitic delay model was too simple
– Calculate parasitic delay for Y falling
• If A arrives latest? 2τ
• If B arrives latest? 2.33τ

2 2 Y
A 2 6C

B 2x 2C

10: Combinational Circuits CMOS VLSI Design 4th Ed. 10

 Inner & Outer Inputs
 Inner input is closest to output (A)
2 2 Y
 Outer input is closest to rail (B)
A 2
 If input arrival time is known B 2

– Connect latest input to inner terminal

10: Combinational Circuits CMOS VLSI Design 4th Ed. 11

 Asymmetric Gates
 Asymmetric gates favor one input over another
 Ex: suppose input A of a NAND gate is most critical
– Use smaller transistor on A (less capacitance)
– Boost size of noncritical input A
Y
reset
– So total resistance is same
 gA = 10/9 2 2
Y

 gB = 2 A 4/3
reset 4
 gtotal = gA + gB = 28/9
 Asymmetric gate approaches g = 1 on critical input
 But total logical effort goes up
10: Combinational Circuits CMOS VLSI Design 4th Ed. 12
 Symmetric Gates
 Inputs can be made perfectly symmetric

2 2
Y
A 1 1
B 1 1

10: Combinational Circuits CMOS VLSI Design 4th Ed. 13

 Skewed Gates
 Skewed gates favor one edge over another
 Ex: suppose rising output of inverter is most critical
– Downsize noncritical nMOS transistor
HI-skew unskewed inverter unskewed inverter
inverter (equal rise resistance) (equal fall resistance)

2 2 1
A Y A Y A Y
1/2 1 1/2

 Calculate logical effort by comparing to unskewed

inverter with same effective resistance on that edge.
– gu = 2.5 / 3 = 5/6
– gd = 2.5 / 1.5 = 5/3
10: Combinational Circuits CMOS VLSI Design 4th Ed. 14
 HI- and LO-Skew
 Def: Logical effort of a skewed gate for a particular
transition is the ratio of the input capacitance of that
gate to the input capacitance of an unskewed
inverter delivering the same output current for the
same transition.

 Skewed gates reduce size of noncritical transistors

– HI-skew gates favor rising output (small nMOS)
– LO-skew gates favor falling output (small pMOS)
 Logical effort is smaller for favored direction
 But larger for the other direction
10: Combinational Circuits CMOS VLSI Design 4th Ed. 15
 Catalog of Skewed Gates
Inverter NAND2 NOR2

2 2 B 4
Y
2 A 4
A 2
unskewed A Y Y
1 guu = 1 B 2 guu = 4/3 1 1 guu = 5/3
gdd = 1 gdd = 4/3 gdd = 5/3
avg = 1
gavg avg = 4/3
gavg gavg
avg = 5/3

2 2 B 4
Y
2 A 4
A 1
HI-skew A Y Y
1/2 gu = 5/6 B 1 guu = 1 1/2 1/2 guu = 3/2
u
gdd = 5/3 gdd = 2 gdd = 3
avg = 5/4
gavg gavg
avg = 3/2 gavg
avg = 9/4

1 1 B 2
Y
1 A 2
A 2
LO-skew A Y Y
1 guu = 4/3 B 2 guu = 2 1 1 guu = 2
gdd = 2/3 gdd = 1 gdd = 1
gavg
avg = 1 gavg
avg = 3/2 gavg
avg = 3/2

10: Combinational Circuits CMOS VLSI Design 4th Ed. 16

 Asymmetric Skew
 Combine asymmetric and skewed gates
– Downsize noncritical transistor on unimportant
input
– Reduces parasitic delay for critical input

A
Y
reset

1 2
Y
A 4/3
reset 4

10: Combinational Circuits CMOS VLSI Design 4th Ed. 17

 Best P/N Ratio
 We have selected P/N ratio for unit rise and fall
resistance (μ = 2-3 for an inverter).
 Alternative: choose ratio for least average delay
 Ex: inverter
– Delay driving identical inverter P
A
– tpdf = (P+1) 1

– tpdr = (P+1)(μ/P)
– tpd = (P+1)(1+μ/P)/2 = (P + 1 + μ + μ/P)/2
– dtpd / dP = (1- μ/P2)/2 = 0

– Least delay for P =
10: Combinational Circuits CMOS VLSI Design 4th Ed. 18
 P/N Ratios
 In general, best P/N ratio is sqrt of equal delay ratio.
– Only improves average delay slightly for inverters
– But significantly decreases area and power

Inverter NAND2 NOR2

2 2 B 2
Y
fastest 1.414 A 2
A 2
A Y Y
P/N ratio 1 gu = 1.15 B 2 gu = 4/3 1 1 gu = 2
gd = 0.81 gd = 4/3 gd = 1
gavg = 0.98 gavg = 4/3 gavg = 3/2

10: Combinational Circuits CMOS VLSI Design 4th Ed. 19

 Observations
 For speed:
– NAND vs. NOR
– Many simple stages vs. fewer high fan-in stages
– Latest-arriving input
 For area and power:
– Many simple stages vs. fewer high fan-in stages

10: Combinational Circuits CMOS VLSI Design 4th Ed. 20