Scribd
Upload
8 views17 pages

DFTS BE 4 II Sem Unit 3

DFTS

Uploaded by

M. Mohd. Sabir Hussain
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
8 views17 pages

DFTS BE 4 II Sem Unit 3

DFTS

Uploaded by

M. Mohd. Sabir Hussain
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 17

Introduction

Design of Fault Tolerant System


Elective III (DFTS)
Unit III
Course description

 Unit 1-Basic of reliability and fault


modelling-test generations
 Unit 2-Fault tolerant design I
 Unit 3-Fault tolerant design II-VLSI chip
scheme
 Unit 4-Self checking-fail safe design-
PLAs
 Unit 5-Design for testability-BIST
Syllabus
 UNIT-III: Fault Tolerant Design-II: Time
redundancy, software redundancy, fail-soft
operation, examples of practical fault tolerant
systems, introduction to fault tolerant design of
VLSI chips.
 Time Redundancy
 Software Redundancy
 Fail soft operations
 Example of Practical Fault Tolerant
Systems (14)
 A scheme for fault tolerant design for
VLSI chip
Time Redundancy

 Time redundancy is commonly used in the


detection and correction of errors caused by
temporary faults or transient fault.
 It involves repetitions or rollback of instruction,
segments of programs or entire program
immediately after a fault us detected.
 Rollback operations requires check points.
 In time redundancy the computation or data
transmission is repeated and the result is compared
to a stored copy of the previous result.
Example

 JPLstar computer
 COPRA
Time redundancy for transient
fault detection
Time redundancy for transient
fault correction
Software Redundancy

 TheN-version programming technique


resembles the N-modular hardware
redundancy
Example
Computer voted Multiprocessor
Computer voted Multiprocessor(C.Vmp):
 It is capable of operating correctly in the presence of
both permanent and temporary faults.
 In basic design it includes separate power distribution
networks, so that parts of the system can be
deactivated while the rest of the system is in
operation.
 It helps in on line maintenance and making the system
highly available.
Block Diagram
 It consist of Processor, Voter and Buses
Operation
 Each processor (DEC LSI -11s) has a memory unit M
and A disk associated with it, the user terminals are
interface via the Serial Line Unit (SLU).
 Voter includes a disagreement detectors one for each
bus, use to monitor the failure in each of the three
parts of the system.
 Voter operate in two modes.
 Broadcast Mode
 Independent Mode

There are trade off between two phases in terms of


reliability and performance.
 Broadcast Mode: The request of one processor bus
broadcast onto all three buses, this mode used for
system initialization and selective triplication of I/O
devices.
 Independent Mode: Here each processor working
separately and interprocessor communication taking
place via parallel interface (links).

 The reliability of CVmp has been measured and


reported in terms of failure record and a failure
recovery data.
Pluribus
 The pluribus system serves as an interface message
processor (IMP) in the ARPA network.
 ARPA – Advanced Research Project Agency based on
TCP/IP Protocol.
 The goal of Pluribus is high availability.
 Pluribus system consist of Processor modules ,
Memory module and I/O modules
Block Diagram
Operation
 Processor module acts as bus for interconnection with
other modules.
 It consist of sub processors and bus coupler.
 Each processor module is connected to each memory
module(32 k to 80 k) via a bus coupler.
 I/O module an arbitrary

You might also like