Department of ECE

VLSI DESIGN
22EC2211A
Topic:

CIRCUIT CHARACTERIZATION
AND PERFORMANCE
ESTIMATION
Session - 5

CREATED BY K. VICTOR BABU

 AIM OF THE SESSION
The session aims to provide a comprehensive understanding of MOS circuits, covering various aspects such as
introduction, delay estimation, logical effort, transistor sizing, power dissipation, interconnect, design margins,
reliability.

INSTRUCTIONAL OBJECTIVES

This Session is designed to:

1. Describe the different types of power dissipation in CMOS Inverter.
2. Demonstrate the static and dynamic power dissipation of a CMOS Inverter.
3. Describe the Area consideration in CMOS Inverter w.r.t power dissipation.

LEARNING OUTCOMES

At the end of this session, you should be able to:

1. Define the different types of power dissipation in the CMOS Inverter.
2. Determine the static and dynamic power dissipation.

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 SESSION INTRODUCTION

“Circuit Characterization and Performance Estimation”

 The session starts with the DC characteristics of CMOS inverter followed by its Dynamic
characteristics.

 The power and area considerations are explained in this session.

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 SESSION DESCRIPTION

POWER AND AREA CONSIDERATIONS:

• We can identify two other issues that play significant roles in inverter design: power consumption and the
chip area occupied by the inverter circuit.

• About one million logic gates can be accommodated on a very large scale integrated (VLSI) chip using 0.5
μm MOS technology, and the circuit density is expected to increase even further in future-generation
chips.

• Since each gate on the chip dissipates power and thus generates heat, the removal of this thermal energy,
i.e., cooling of the chip, becomes an essential and usually very expensive task.

• It is very important to reduce the amount of power dissipated by the circuit in both DC and dynamic
operation.

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 SESSION DESCRIPTION

DC power dissipation of an inverter circuit:

• The DC power dissipation of an inverter circuit can be calculated as the product of its power supply voltage
and the amount of current drawn from the power supply during steady state.

• Notice that the DC current drawn by the inverter circuit may vary depending on the input and output
voltage levels.

• Assuming that the input voltage level corresponds to logic "0” during 50% of the operation time and to logic
" 1 " during the other 50%, the overall DC power consumption of the circuit can be estimated as follows:

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Dynamic power dissipation of an inverter circuit:

• In a CMOS inverter, the dynamic power dissipation occurs when the load capacitor is charged and
discharged.

• When the load capacitor is charged, it takes some energy from the power supply; part of this energy is
stored in the load capacitor and the remainder is dissipated across the pMOS transistor.

• Next, during the discharge of the load capacitor, the stored energy is discharged through the nMOS
transistor.

• Dynamic power dissipation has maximum contribution in the total power dissipation.

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Dynamic power dissipation of an inverter circuit:

• The average energy dissipated over one switching cycle is calculated as follows:

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 SESSION DESCRIPTION

Dynamic power dissipation of an inverter circuit:

If the circuit switching frequency is f, then the dynamic power dissipation is determined as follows:

where α (0 < α < 1) is the activity factor.

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Area Considerations:

• To reduce the chip area occupied by the inverter circuit, it is necessary to reduce the area of the MOS
transistors used in the circuit.

• As a practical measure, we use the gate area of the MOS transistor, i.e., the product of W and L.

• Thus, an MOS transistor has minimum area when both of the gate (channel) dimensions are made as
small as possible within the constraints of the particular technology.

• It follows that the ratio of the gate width to gate length (W/L) should also be as close to unity as
possible, in order to achieve minimum transistor area.

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 SESSION DESCRIPTION

Delays:

• Inverter propagation delay: time delay between input and output signals

• Typical propagation delays: < 100 ps Propagation delay denoted as tp

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 SESSION DESCRIPTION

Propagation delay high-to-low (tphl):

• During early phases of discharge, NMOS is saturated and PMOS is cut-off.

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Propagation delay high-to-low (tphl):

Time to discharge half of charge stored in CL:

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Propagation delay low-to-high(tplh):

• During early phases of discharge, PMOS is saturated and NMOS is cut-off.

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Time to charge to half of final charge on CL:

During early phases of discharge, PMOS is saturated and NMOS is cut-off.

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RISE/FALL TIME:

Rise time (tr):

 Rise time (tr) is the time, during transition, when output switches from

10% to 90% of the maximum value.

 Many designs could also prefer 30% to 70% for rise time

Fall time (tf):

 Fall time (tf) is the time, during transition, when output switches from 90% to 10% of the
maximum value.

 Many designs could also prefer 70% to 30% for fall time

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RISE/FALL TIME:

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Noise Margins:

• Practical inverter circuits experience external disturbances leading to extra voltage on the signal lines.
Such unwanted additional voltage is termed as noise.

• If the noise in a digital circuit exceeds certain margins, known as noise margins, the desired logic levels
are changed.

• We derive expressions to define noise margins for logic ‘0’ and logic ‘1’.

• In practical inverter circuits, the maximum input low level is V IL and the maximum output low level is

VOL. Therefore, if VIL > VOL, then there is a margin in the input voltage for logic ‘0’, which can be
allowed without causing any change in the output voltage.

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Noise Margins:

Hence, the noise margin for logic ‘0’ (NML) is defined as follows:

NML = VIL − VOL

Similarly, the noise margin for logic ‘1’ (NMH) is defined as follows:

NMH = VOH − VIH

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 SESSION DESCRIPTION

Noise Immunity:

• The ability of an apparatus or system to perform its functions when interference (noise) is present.

• Noise immunity is rated according to the noise intensity at which the disruption of the equipment's
functions is still within permissible limits.

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 SESSION DESCRIPTION

Noise Immunity:

• To illustrate the effect of noise on the circuit reliability, we will consider the circuit consisting of three
cascaded inverters, as shown in Figure 2.13.

• Assume that all inverters are identical, and that the input voltage of the first inverter is equal to VOH, i.e.,
a logic “1”.

• The output voltage of the first inverter will be equal to VOL corresponding to a logic "0" level.

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Noise Immunity:

• Now, this output signal is being transmitted to the next inverter input via an interconnect, which could be a
metal or polysilicon line connecting the two gates.

• Since on-chip interconnects are generally prone to signal noise, the output signal of the first inverter will
be perturbed during transmission.

• Consequently, the voltage level at the input of the second inverter will be either larger or smaller than V OL.

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Noise Immunity:

• If the input voltage of the second inverter is smaller than V OL this signal will be interpreted correctly as a
logic "0" input by the second inverter.

• On the other hand, if the input voltage becomes larger than V IL as a result of noise, then it may not be
interpreted correctly by the inverter.

• Thus, we conclude that VIL is the maximum allowable voltage at the input of the second inverter, which is
low enough to ensure a logic "1" output
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Noise Immunity:

• Now consider the signal transmission from the output of the second inverter to the input of the third
inverter, assuming that the second inverter produces an output voltage level of V OH.

• As in the previous case, this output signal will be perturbed because of noise interference, and the voltage
level at the input of the third inverter will be different from V OH.

• If the input voltage of the third inverter is larger than V OH, this signal will be interpreted correctly as a
logic " 1 " input by the third inverter.
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Noise Immunity:

• If the voltage level drops below VIH due to noise, however, the input cannot be interpreted as a logic "1”.

• Consequently, VIH is the minimum allowable voltage at the input of the third inverter, which is high
enough to ensure a logic "0" output.

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 SESSION DESCRIPTION

PARASITIC CAPACITANCE:

• These are unwanted capacitances, but still are part of the transistor. Together with the resistances in the
circuit, they put an upper limit to the speed of the transistor.

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 SESSION DESCRIPTION

Types of parasitic capacitances:

• C1 and C2 are capacitances created by the

depletion regions between source/drain and bulk.

• C3 is the depletion capacitance between the

channel and bulk.

• C4 and C5 are capacitances caused by the overlap

between the gate and the source/drain diffusions.

• Finally, C6 is the oxide capacitance between gate

and the channel and is split between drain and
source depending on the region of operation of the
transistor.

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 SESSION DESCRIPTION

1. Junctions depletion capacitances

C1 and C2 are capacitances created by the depletion regions of the
junctions between
source/drain and bulk. These junctions are three-dimensional.
2. Overlap and gate-channel capacitances
 C4 and C5 are overlap capacitances and are only proportional to
the width of the transistor.
 C6 is the gate-channel capacitance and its total value is split
between drain and source in a way that depends on the region of
operation of the transistor.
 Cov - Overlap capacitance per unit length (fF/μm).
 Cox - Gate to channel capacitance per unit area (fF/μm2).
 CGS and CGD have a base value of the overlap capacitance WC ov.
 To that we add the gate to channel capacitance WLC ox according
to the region of operation.

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 SESSION DESCRIPTION

3. Channel-bulk depletion capacitance

 This capacitance is only relevant in subthreshold regime.

 In strong inversion, the channel is being driven and shields the

transistor from this capacitance.

 However, in subthreshold there is no channel and this capacitance

is in series with the oxide capacitance. Furthermore, CGS and CDS
are made of only the overlap capacitance and they are small.

Consider the cascade connection of two CMOS inverter circuits

shown in Figure 2.24.

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 SESSION DESCRIPTION

3. Channel-bulk depletion capacitance

The various parasitic capacitances are:

1) Gate-Drain capacitance (Cgd12)

2) 2) Diffusion capacitances (Cdb1, Cdb2)

3) 3) Wiring capacitance (Cw)

4) 4) Gate capacitances of fan-out (Cg3, Cg4).

The total load capacitance now is given as,

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 SESSION DESCRIPTION

3. Channel-bulk depletion capacitance

In addition, we also consider the lumped interconnect capacitance Cint, which represents the parasitic
capacitance contribution of the metal or polysilicon connection between the two inverters.

 It is assumed that a pulse waveform is applied to the input of the first-stage inverter.

 We wish to analyze the time-domain behavior of the first-stage output, Vout

 The problem of analyzing the output voltage waveform is fairly complicated, even for this relatively
simple circuit, because a number of nonlinear, voltage-dependent capacitances are involved.

 To simplify the problem, we first combine the capacitances seen in Figure 2.24, into an equivalent
lumped linear capacitance, connected between the output node of the inverter and the ground.

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 SESSION DESCRIPTION

Lumped output load capacitance.:

• The first-stage CMOS inverter is shown with

the single lumped output load capacitance C load
in Figure 2.25.

• Now, the problem of analyzing the switching

behavior can be handled more easily.

• The delay times calculated using C L may

slightly overestimate the actual inverter delay,
but this is not considered a significant
deficiency in a first-order approximation.

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 ACTIVITIES/ CASE STUDIES/ IMPORTANT FACTS RELATED TO THE
SESSION

Activities:
Design any circuits using CMOS inverter considering low power dissipation.
Articles:
a. R. X. Gu and M. I. Elmasry, "Power dissipation analysis and optimization of deep submicron CMOS digital circuits," in
IEEE Journal of Solid-State Circuits, vol. 31, no. 5, pp. 707-713, May 1996, doi: 10.1109/4.509853.
Case Studies:
a. CMOS Power Dissipation and Trends (https://www.ece.ucdavis.edu/~ramirtha/EEC216/W08/lecture1_updated.pdf)

b. CMOS inverter propagation delay. (http://www.ece.sunysb.edu/~oe/Leon/ESE314F12/Lab09.pdf)

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 EXAMPLES

Most portable systems, such as cellular communication devices and laptop and palmtop computers, operate
from a limited power supply, and the extension of battery-based operation time is a significant design goal.

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 SUMMARY

The DC characteristics of CMOS inverter followed by its Dynamic characteristics are described in this
session. The power and area considerations are explained.

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 SELF-ASSESSMENT QUESTIONS

1. How is the static power dissipation is almost zero in CMOS Inverter?

2. List out the sources of static and dynamic power consumption.

3. Write the expression for the average propagation delay of CMOS Inverter.

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 TERMINAL QUESTIONS

a. Derive the expression for dynamic power dissipation in CMOS Inverter.

b. Briefly explain the requirements to reduce the area of the MOS transistors used in the circuit.

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 REFERENCES FOR FURTHER LEARNING OF THE SESSION

Text Books:
1.Douglas A. Pucknell& Kamran Eshraghian, Basic VLSI Design, PHI, 3rd Ed., 2011
2. Neil H.E. Weste, David Harris, Ayan Banerjee, CMOS VLSI Design, A Circuits and Systems
Perspective, Pearson Education, 4th Ed., 2011
3. Sung-Mo Kang, Yusuf Leblebici, CMOS Digital Integrated Circuits Analysis and Design, Tata Mc-
Graw-Hill, 3rd Ed., 2003
Reference Books:
1. Jab M. Rabaey, Anantha Chandra Kasan, Borivoje Nikolic, Digital Integrated Circuits - A Design
Perspective, PHI, 2nd Ed., 2012
2. Michal John Sebastian Smith, Application-Specific Integrated Circuits, Pearson Education, 6th Ed.,
2009

Sites and Web links:

1. https://archive.nptel.ac.in/courses/106/105/106105034/

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 THANK YOU

Team – VLSI Design

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