VerilogHDL

(Combinational Circuits)
“A common approach is to design each IC chip, using an
HDL, and then verify system functionality via simulation”
Introduction
Digital circuit design evolved rapidly over the last 25 years.
The earliest digital circuits designed with  vacuum tubes and
transistors.

Later ICs Invented logic gates placed on a single chip.

The first IC chipsSSI(Small Scale Integration) 10 gates

As technologies became sophisticated, designers able to place circuits

with 100 of gates on a chip MSI (Medium Scale Integration) chips.

With the advent of LSI (Large Scale Integration), designers could put
1000 of gates on a single chip.
 At this point, design processes started getting very complicated, and
designers felt the need to automate these processes.

Computer Aided Design (CAD)' techniques began to evolve.

Chip designers began to use circuit and logic simulation techniques to
verify the functionality of building blocks of the order of about 100
transistors.
The circuits were still tested on the breadboard, and the layout was
done on paper or by hand on a graphic computer terminal.
With the advent of VLSI (Very Large Scale Integration) technology,
designers could design single chips with more than 100,000
transistors.
Because of the complexity of these circuits, it was not possible to
verify these circuits on a breadboard.

Computer-aided techniques became critical for verification and

design of VLSI digital circuits.
Computer programs to do automatic placement and routing of
circuit layouts also became popular.

“Logic simulators came into existence to verify the functionality of

these circuits before they were fabricated on chip”
 Design of Logic Circuits
Manual methods  Suitable for small circuit

Computer based design tools  suitable for practical circuit

(reduce the risk of producing a flawed design)

Prototype ICs are too expensive and time consuming

Modern design tools  uses hardware description language to

describe, design and test a circuit in before it is ever manufacture

Problem  Solution  Describe

Design
Test
 Typical design flow for designing VLSI IC circuits

Design
entity
functional
verification
Logical
synthesis
 Timing
verification
& fault
simulation
In any design  Specifications are written first.
 Specifications describe abstractly the functionality, interface,
and overall architecture of the digital circuit
Behavioral description is then created to analyze the
design in terms of functionality, performance, compliance to standards,
and other high-level issues, can be written with HDLs.

Behavioral description is manually converted to an RTL description in

an HDL. The designer has to describe the data flow that will implement
the desired digital circuit.
 From this point onward, the design process is done with the
assistance of CAD tools.
Logic synthesis tools convert the RTL description to a gate-level netlist.
Gate-level net-list is a description of the circuit in terms of gates and
connections between them.
The gate-level net-list is input to an Automatic Place and Route
tool, which creates a layout.
The layout is verified and then fabricated on chip.
 Hardware description languages (HDLs)
Verilog and VHDL are computer based languages that describes
the hardware of digital systems in a textual form
It is similar to normal computer programming language such as
C but is specifically oriented to describing hardware structure and
the behavior of logic circuits
It is used to represent logic diagrams, truth tables, Boolean
expression and complex abstractions of the behavior of a digital
system
It describes a relationship b/n signals that are the inputs to a
circuit and the signals that are the outputs of the circuit
HDL is used in several major steps in the design flow of an ICs

“Design is first described in HDL and then verified by

simulating the design and checking it with a test bench
which is also written in HDL”
 Structure of the verilog module
Names of the inputs and outputs can be
Pre-defined User-defined
declared in any order

module half_adder (a, b, s, cout);

keyword
Identifiers

Input a, b;
Signal declaring statements
Output s, cout;

assign s = a ^ b; Signal assignment statements relation

assign cout = a & b ; b/n i/p and o/p

endmodule // pre-defined endmodule used to terminate

the module
Verilog ports  input, output, inout(bidirectional bus)
Verilog logical operators :
~  NOT operator
&  AND operator Bit-wise
| OR operator operators
~& NAND operator Ex: y= a and b
~| NOR operator y=a&b
^  EX-OR operator
~^ EX-NOR operator

&&  logical AND Boolean

|| logical OR Operators
!  logical NOT Ex : y = ab
y = a && b
Verilog Reduction operators :
~  Reduction NOT operator
&  Reduction AND operator
| Reduction OR operator
~& Reduction NAND operator
~| Reduction NOR operator
^  Reduction EX-OR operator
~^ Reduction EX-NOR operator

Ex: y= &x
if x =1010 then y = (1 & 0 & 1 & 0)
Verilog Relation operators :
==  Equality
!=  Inequality
===  Equality inclusive
!==  Inclusive inequality
<  less-than
<=  less-than or equal
>  greater-than
>=  greater-than or equal
{ }  concantation
? !  conditional
Verilog arithmetic operators :
+A+B
-A-B
*A*B
/A/B
%A%B
**  A ** B ---Exponential operator

Verilog shift operators :

A << 1  A shift one position left
A << 2  A shift two position left
A >> 1  A shift one position right
A >> 2  A shift two position right
 Verilog Data types
(i) Nets are declared by the pre-defined keyword wire
Ex: wire sum;
wire s1 = 1’b0;
a w
c
b
(ii) Registers  stores values until they are updated
data storage elements
Registers are declared by keyword reg
Ex: reg sum;
(iii) Vectors  are multiple bits. A register or a net can be
declared as a vector.
Vectors are declared by brackets [ ]
Ex: wire [3:0] a = 4’b1010;
reg [7:0] total = 8’d12;
 (iv) Integers  are declared by the pre-defined keyword
integer

Ex : integer no_bits;
declares no_bits as an integer
“Registers declared as data type reg store values as unsigned
quantities, whereas integers store values as signed quantities”
(v) Real (floating point)  are declared by the pre-
defined keyword real

Ex : 2.4, 56.3 and 5e12 = 5x1012

real weight
(vi) parameters represent global constants
Ex : module comp_ckt(x,y,xgty,xlty,xeqy)
parameter N =3;
input [N:0]x,y;
(vii) Arrays  parameter N = 3;
parameter M = 3;
reg [M:0] b [0:N];
(viii) String  Strings can be stored in reg. The width of the
register variables must be large enough to hold the string.
Each character in the string takes up 8 bits (1 byte)
reg [8*18:1] string-value; //Declare a variable that is l8 bytes
wide initial
string-value = "Hello Verilog World"; / / String can be stored
/ / in variable
 Types of descriptions

(i) Structural description:

- Structural description model the system as
components or gates
- This description is identified by the presence of the
keyword component such as and, or , not in the
module
module snot1(a, b);
input a;
output b;
not (b, a);
endmodule
(ii) Data flow description:
- This description model describes how the system
signals flow from the inputs to the outputs
- This description is done by writing the Boolean
functions of the outputs
- The data flow statements are concurrent, their
execution is controlled by events
module dnot1(a, b);
input a;
output b;
assign b = ~a; //assign b = !a;
endmodule
(iii) Behavioral description:
- Behavioral description model the system as to how
the outputs behave with the inputs
- The definition of behavioral description is one
where the module includes the pre-defined word
always or initial
module bnot1(a, b);
input a;
output b;
reg b;
always @ (*)
begin
b = ~ a;
end
endmodule

(iV) Mixed mode description: combination of above three

Gate delays  gate delay b/n i/p and o/p
timescale 1ns/100ps

Time delay Precision

module pdsnot1(a, b);

input a;
output b; Will get o/p after 30ns
not # (30) (b, a);
endmodule
Vector
module vbsnot1(a, b);
input[3:0] a;
output[3:0] b;
assign b = a;
endmodule
 module andgate(a, b, c); Test bench
input a,b; module testbench_andgate;
output c; reg a,b;
assign c = a & b; wire c;
endmodule andgate DUT(a,b,c);
module testbench_andgate; initial
reg a,b; begin
wire c; $dumpfile(“andgate.vcd”);
andgate DUT(a,b,c); $dumpvars(1,testbench_andgate);
initial $monitor(a,b,c);
begin a=0;b=0;
a=0;b=0; #5 a=0;b=1;
#50 a=0;b=1; #5 a=1;b=0;
#50 a=1;b=0; #5 a=1;b=1;
#50 a=1;b=1; #5 $finish;
end end
initial #100 $finish endmodule
Verilog code in structural modeling for all the basic gates

module sgates(a, b, y1,y2,y3,y4,y5,y6,y7);

input a,b;
output y1,y2,y3,y4,y5,y6,y7;
o/p first then i/ps

not (y1,a);
and (y2,a,b);
or (y3,a,b);
nand (y4,a,b);
nor (y5,a,b);
xor (y6,a,b);
xnor (y7,a,b);

endmodule
Verilog code in dataflow modeling for all the basic gates
module dgates(a, b, y1,y2,y3,y4,y5,y6,y7);

input a,b;
output y1,y2,y3,y4,y5,y6,y7;

assign y1 = ~a;
assign y2 = a & b;
assign y3 = a | b;
assign y4 = ~(a & b);
assign y5 = ~(a | b);
assign y6 = a ^ b;
assign y7 = ~(a ^ b);

endmodule
Verilog code in behavirol modeling for all the basic gates
module bgates(a, b, y1,y2,y3,y4,y5,y6,y7);

input a,b;
output y1,y2,y3,y4,y5,y6,y7;

always @(a,b)

begin
y1 = ~a;
y2 = a & b;
y3 = a | b;
y4 = ~(a & b);
y5 = ~(a | b);
y6 = a ^ b;
y7 = ~(a ^ b);
end
endmodule
 Verilog code in dataflow modeling for all the vectored basic gates
module vdgates(a, b, y1,y2,y3,y4,y5,y6,y7);

input [3:0] a,b;

output [3:0] y1,y2,y3,y4,y5,y6,y7; Vectored NAND gates

a[0]
assign y1 = ~a; C[0]
b[0]
assign y2 = a & b;
assign y3 = a | b;
a[1]
assign y4 = ~(a & b); C[1]
b[1]
assign y5 = ~(a | b);
assign y6 = a ^ b; a[2] C[2]
assign y7 = ~(a ^ b); b[2]

endmodule a[3]
C[3]
b[3]
 Verilog code in structural modeling for the given logic diagram
(gate level description)

A w1
G1
B G3 D

C G2 E

module logic_dia(A,B,C,D,E); module logic_dia(A,B,C,D,E);

input A,B,C; input A,B,C;
output D,E; output D,E;
wire w1; wire w1;
and G1(w1,A,B); and #(30)G1(w1,A,B);
not G2(E,C); not #(10)G2(E,C);
or G3(D,w1,E); or #(20)G3(D,w1,E);
endmodule endmodule
 Verilog code in structural modeling for the given logic diagram

A w1
C
B

module logic_dia(A,B,C);
input A,B;
output C;
reg w1,C;
always @(*)
begin
w1 = a&b;
C = ~w1;
end
endmodule
Verilog code to realize the following code
(i) y1 = AB + C’
(ii) y2 = A + BC + B’D
(iii) y3 = B’C + BC’D’

module bexp(A,B,C,D,y1,y2,y3);

input A,B,C,D;
output y1,y2,y3;

assign y1 = (A&&B) || (!C);

assign y2 = A || (B && C) || ((!B) && D);
assign y3 = ((!B) && C) || (B && (!C) && (!D));

endmodule
 Verilog code to realize the user defined primitive
(Truth table) D = Σ(0,2,4,6,7)
primitive UDP_02467(D,A,B,C);
output D;
input A,B,C;
table
A B C : D
0 0 0 : 1
0 0 1 : 0
0 1 0 : 1
0 1 1 : 0
1 0 0 : 1
1 0 1 : 0
1 1 0 : 1
1 1 1 : 1
endtable
endprimitive
 Verilog code to realize the instantiate primitive

A E
UDP_02467
B
C
F
D
Module block_dia(E,F,A,B,C);
input A,B,C;
output E,F;

UDP_02467 (E,A,B,C);
and (F,E,D);

endmodule
 Verilog code to realize half adder in structural modeling

module ha(a, b, sum, cout);

a
b sum
input a,b;
output sum, cout;

cout xor (sum,a,b);

and (cout,a,b);

endmodule
 Verilog code to realize half adder in dataflow modeling

module ha(a, b, sum, cout);

a
b sum
input a,b;
output sum, cout;

cout assign sum = a^b;

assign cout = a&b;

endmodule
 Verilog code to realize half adder in behavioral modeling

module ha(a, b, sum, cout);

a
b sum
input a,b;
output sum, cout;

cout reg sum, cout;

always @(a,b)
begin
sum = a^b;
cout = a&b;
end
endmodule
 Verilog code to realize full adder in structural modeling
module fa(a, b, cin, sum, cout);
a s1
b sum input a,b,cin;
cin output sum, cout;
c1 wire s1,c1,c2,c3;

cout xor (s1,a,b);

c2
xor (sum,s1,cin);
and (c1,a,b);
c3 and (c2,b,cin);
and (c3,cin,a);
or (cout,c1,c2,c3);

endmodule
 Verilog code to realize full adder in dataflow modeling
module fa(a, b, cin, sum, cout);
a s1
b sum input a,b,cin;
cin output sum, cout;
c1 wire s1,c1,c2,c3;

cout assign s1= a^b;

c2
assign sum = s1^cin;
assign c1 = a&b;
c3 assign c2 = b&cin;
assign c3 = cin&a;
assign cout = c1|c2|c3;

endmodule
 Verilog code to realize full adder in behaviral modeling
module fa(a, b, cin, sum, cout);
a s1
b sum input a,b,cin;
cin output sum, cout;
c1 reg s1,c1,c2,c3,sum,cout;

c2 cout always @ (*)

begin
s1= a^b;
c3 sum = s1^cin;
c1 = a&b;
c2 = b&cin;
c3 = cin&a;
cout = c1|c2|c3;
 Verilog code to realize full adder using two half adder in
structural modeling

a s1
b sum
c1 c2
cout
cin
module fa(a, b, cin, sum, cout);
input a,b,cin;
output sum, cout;
wire s1,c1,c2;
xor (s1,a,b);
and (c1,a,b);
xor (sum,s1,cin);
and (c2,s1,cin);
or (c ,c1,c2);
 Verilog code to realize full adder using two half adder in
dataflow modeling

a s1
b sum
c1 c2
cout
cin
module fa(a, b, cin, sum, cout);
input a,b,cin;
output sum, cout;
wire s1,c1,c2;
assign s1 = a^b;
assign c1 = a&b;
assign sum = s1^cin);
assign c2 = s1&cin;
assign c = c1&c2;
Verilog code to realize full adder using 2-half adder in structural
modeling based on instantiation

Module full_adder(a, b, cin, sum, cout);

input a, b, cin;
output sum, cout;
module half_adder(a, b, sum, cout);
wire s1,c1,c2;
input a,b;
half_adder ha1(a,b,s1,c1); output sum, cout;
half_adder ha2(s1,cin,sum,c2);
or (cout,c1,c2); xor (sum,a,b);
endmodule and (cout,a,b);

endmodule
Verilog code to realize 4-bit full adder (cascading of 4 FAs) in structural
modeling based on instantiationModule full_adder(a, b, cin, sum, cout);
input a, b, cin;
Module 4-bitfa(a, b, cin, sum, cout); output sum, cout;

input[3:0]a,b; wire s1,c1,c2;

input cin;
output[3:0]sum; half_adder ha1(a,b,s1,c1);
output cout; half_adder ha2(s1,cin,sum,c2);
or (cout,c1,c2);
wire c1,c2,c3; endmodule
module half_adder(a, b, sum, cout);
Full_adder fa1(a[0],b[0],Cin,sum[0],c1);
input a,b;
Full_adder fa2(a[0],b[0],Cin,sum[0],c1);
output sum, cout;
Full_adder fa3(a[0],b[0],Cin,sum[0],c1);
Full_adder fa4(a[0],b[0],Cin,sum[0],c1); xor (sum,a,b);
and (cout,a,b);
endmodule
 Verilog code to realize 4-bit full adder in data flow modeling
Using concatenation operator
Module vfa(a, b, cin, sum, cout);

input[3:0] a, b;
input cin;
output [3:0]sum;
output cout;

assign {cout, sum} = a + b + cin; //concatenation operator

endmodule
Verilog code to realize full adder using 2-half adder in mixed modeling
Module fa-mixed(a, b, cin, sum, cout);

input a,b,cin;
output sum,cout;

wire s1,c1,c2;
reg cout;

xor x1(s1,a,b);
and a1(c1,a,b);

assign sum = s1^cin;

assign c2 = s1&cin;

always @(c1,c2)
begin
cout = c1 | c2;
Verilog code to realize 8-bit full adder (cascading of two 4-bit FAs) in
structural modeling based on instantiation
Module 8-bitfa(x, y, cin, cout,sum);

input[7:0]x,y;
input cin;
output[7:0]sum;
output cout; instantiate

wire cout1;

four_bit_adder adder_a(x[3:0], y[3:0], Cin, cout1 , sum[3:0];

four_bit_adder adder_b(x[7:0], y[7:0], Cin, cout1 , sum[7:0];
endmodule
Module four_bit_adder(x, y, cin, cout, sum);
input [3:0]x, y;
input cin;
output [3:0]sum;
output cout;

wire c1,c2,c3;

full_adder fa_1(x[0],y[0],cin,c1,sum[0]);
full_adder fa_2(x[1],y[1],c1,c2,sum[1]);
full_adder fa_3(x[2],y[2],c2,c3,sum[2]);
full_adder fa_4(x[3],y[3],c3,cout,sum[3]);

endmodule
module full_adder(x, y, cin, cout, sum);

input x,y,cin;
output sum, cout; Module half_adder(x, y, c, s);

wire s1,c1,c2; input x,y;

output c,s;
half_adder ha_1(x, y, c1, s1)
half_adder ha_2(Cin, s1,c2,sum); xor (s,x,y);
and (c,x,y);
or (cout,c1,c2);
endmodule
endmodule
Verilog code to realize n-bit adder in behavioral modeling
Using concatenation operator

Module nbit_adder(a, b, cin, s, cout);

parameter m = 3;

input [m-1:0] a;
input [m-1:0] b;
input Cin;
output reg [m-1:0] s;
output reg cout;

always @ (*)
{ Cout, S} = a + b + Cin; //Concatenation operator
endmodule
 Conditional operator

Condition-expression ? True statement : false statement

if(condition-expression) true statement

else false statement

Ex: 2 to 1 MUX

assign out = selection ? Input1 : input0;

if selection = 0, out = input0

= 1, out = input1
 Verilog code to realize 2-bit and 4-bit comparator in data flow
modeling Using conditional operator
module 2bc( input[1:0]A, input[1:0]B, output E, G, L);

assign G = ( A > B ) ? 1’b1 : 1’b0;

assign L = ( A < B ) ? 1’b1 : 1’b0;
assign E = ( A == B ) ? 1’b1 : 1’b0;

endmodule
module 4bc( input[3:0]A, input[3:0]B, output E, G, L);

assign G = ( A > B ) ? 1’b1 : 1’b0;

assign L = ( A < B ) ? 1’b1 : 1’b0;
assign E = ( A == B ) ? 1’b1 : 1’b0;

endmodule
Verilog code to realize n-bit comparator in data flow modeling Using
conditional operator

module nbc(a,b, E, G, L);

parameter N = 4;
input [N-1:0]a,b;
output E,G,L;

assign G = ( A > B ) ? 1’b1 : 1’b0;

assign L = ( A < B ) ? 1’b1 : 1’b0;
assign E = ( A == B ) ? 1’b1 : 1’b0;

endmodule
Verilog code to realize n-bit comparator in behavioral modeling
module nbc (x, y, g, e, l);
parameter m = 2;
input [m-1:0]x,y;
output reg g, e, l;
always @ (*)
begin
if (x > y) else
begin begin
g=1; g=0;

e=0; e=1;
l=0; l=0;
end end
if (x < y) end
begin endmodule
g=0;
e=0;
l=1;
 Verilog code to realize 4-bit magnitude comparator in dataflow
modeling

module fbmc(Iagtb, Ialtb, Iaeqb, a, b, Oagtb, Oaltb, Oaeqb);

input [3:0] a, b;
input Iagtb, Ialtb, Iaeqb;
output Oagtb, Oaltb, Oaeqb ;

assign Oaeqb = (a==b) && (Iaeqb == 1);

assign Oagtb = (a > b) || ((a==b) && (Iagtb==1));
assign Oagtb = (a < b) || ((a==b) && (Ialtb==1));

endmodule
Verilog code to realize binary to grey code and vice-versa conveter in
dataflow modeling
module bin2grey( input[3:0]bin, output[3:0]G); G3 = B3
assign G[3] = bin[3]; G2 = B3 ʘ B2
assign G[2] = bin[3] ^ bin[2]; G1 = B2 ʘ B1
assign G[1] = bin[2] ^ bin[1];
assign G[0] = bin[1] ^ bin[0];
G0 = B1 ʘ B0

endmodule
module grey2bin( input[3:0]G, output[3:0]bin);
B3 = G3 assign bin[3] = G[3];
B2 = G3 ʘ G2 assign bin[2] = G[3] ^ G[2];
assign bin[1] = G[3] ^ G[2] ^ G[1];
B1 = B2 ʘ G1 assign bin[0] = G[3] ^ G[2] ^ G[1] ^ G[0];
B0 = B1 ʘ G0
endmodule
 Verilog code to realize n-bit binary to grey code and vice-versa
conveter in behavioral modeling
module nb2g( x,y);

parameter n = 4;
input [n-1:0]x;
output reg[ n-1:0]y;

integer i;

always @ (x)
begin
y[n-1] = x[n-1];
for(i=0; i < n; i++)
y[n-1-i] = x[n-i] ^ x[n-1-i];
end

endmodule
 Verilog code to realize BCD to excess-3 converter in behavioral
modeling
E3 = B2B0 + B2B1 + B3 E2 = B2’(B1+B0)+B2B1’B0’
= B2(B0+B1)+B3
E1 = B1’B0’ + B1B0 E0 = B0’
=(B1 ʘ B0)’
module bcd2ex3( input[3:0]b, output reg[3:0]e);

always @(b)
begin
e[3] = b[3] | (b[2] & b[0]) | (b[2] & b[1]);
e[2] = (b[2] & (~b[1]) & (~b[0])) | (~b[2] & b[0]) | (~b[2] & b[1]);
e[1] = ~(b[1] ^ b[0]);
e[0] = ~b[0];
end

endmodule
 Verilog code to realize excess-3 to BCD converter in behavioral
modeling
B3 = E3E2 + E3E2E0
B2 = E0(E1E2+E1’E3)+E2’E0’
=E3(E1 E0+E2)
B1 = E1’E0 + E1E0’ B0 =E0’
= E1 ʘ E0

module ex32bcd( input[3:0]e, output reg[3:0]b);

always @(e)
begin
b[3] = (e[3] & (e[2]) | (e[3]) & e[1] & e[2]);
b[2] = ((~e[2] & e[1]) | (e[2] & e[1] & e[0]) | (~e[2] & (~e[1]));
b[1] = e[1] ^ e[0];
b[0] = ~e[0];
end
endmodule
 Verilog code to realize 9-bit generator using a reduction operator

oP
X[8:0]
eP
module pg(x, ep, op);

input [8:0] x;
output ep, op;

assign ep = ^x; //even parity

assign op = ~ep; //odd parity

endmodule
Verilog code to realize an all-bit zero/one detector using a reduction
operator

zero

X[7:0] one
module nzo(x, zero, one);

input [7:0] x;
output zero, one;

assign zero = ~ ( |x ); //zero detector

assign one = & x; //one detector

endmodule
 Verilog code to realize shift operators
Module logical_shift; Module arithmetic_shift;
reg[3:0] start, result; reg signed [3:0] start, result;
initial initial
begin begin
start = 4’b0001; //0001 start = 4’b1000; //1000
result = (start <<2); //0100 result = (start >>>2); //1110
end end
endmodule endmodule

Module arithmetic_shift(x,y,z);
input signed [3:0] x;
output [3:0] y;
output signed [3:0] z;

assign y = x>>1; //logical right shift

assign z = x>>>1; //arithmetic shift
endmodule
 Verilog code to realize 2:1 MUX in structural modeling
S0 I I
0 1
module 2t1mux(y, S0, I0, I1);

input S0, I0, I1;

output y;
w1 w3 wire w1, w2, w3;
y not (w1, S0);
and (w3, w1, I0);
and (w2, S0, I1);
w2 or (y, w2, w3);

Y = S0’I0 + S0I1 endmodule

 Verilog code to realize 2:1 MUX in dataflow modeling

module 2t1mux(y, S0, I0, I1); Y = S0’I0 + S0I1

module 2t1mux(y, S0, I);
input S0, I0, I1;
output y; input S0
input [1:0] I;
wire w1, w2, w3; output y;

assign w1 = ~S0; assign y = ((~S0) & I[0]) | (S0 & I[1]);

assign w3 = w1 & I0;
assign w2 = S0 & I1; endmodule
assign y = w2 | w3;

endmodule
Verilog code to realize 2:1 MUX in dataflow modeling using
conditional operator
module 2t1mux(y, S0, I0, I1);

input S0, I0, I1;

output y;

assign y = S0 ? I1 : I0;

endmodule
Verilog code to realize 2:1 MUX in behavioral modeling using case
statement

module 2t1mux(input[1:0]I, input S0, output reg y);

always @(I, S0)

begin
case (S0)
1’b0 : y = I[0];
1’b1 : Y = I[1];
endcase
end
endmodule
 Verilog code to realize 4:1 MUX in structural modeling
S1 S0
I0 I1 I2 I3 Z= S1’S0’I0+S1’S0I1
+S1S0’I2+S1S0I3
w1 w3
w2
w4 y
w5

w6
Verilog code to realize 4:1 MUX in structural modeling
module 4t1mux(y, S0, S1, I0, I1 , I2, I3);

input S0, I0, I1;

output y;

wire w1, w2, w3, w4, w5, w6;

not (w1, S1);

not (w2, S0);
and (w3, w1, w2, I0);
and (w4, w1, S0, I1);
and (w5, S1, w2, I2);
and (w6, S1, S0, I3);
or (y, w3, w4, w5, w6);

endmodule
Verilog code to realize 4:1 MUX in dataflow modeling
module 4t1mux(y, S0, S1, I0, I1 , I2, I3);

input S0, I0, I1;

output y;

wire w1, w2, w3, w4, w5, w6;

assign w1 = ~S1;
assign w2 = ~S0;
assign w3 = w1 & w2 & I0;
assign w4 = w1 & S0 & I1;
assign w5 = S1 & w2 & I2;
assign w6 = S1 & S0 & I3;
or y = w3 | w4 | w5 | w6;

endmodule
Verilog code to realize 4:1 MUX in dataflow modeling

Z= S1’S0’I0+S1’S0I1 +S1S0’I2+S1S0I3
module 4t1mux(y, S, I);

input[1:0]S;
input [3:0] I;
output y;

assign y = ((~S[1]) & (~S[0]) & I[0])

| ((~S[1]) & S[0] & I[1])
| (S[1] & (~S[0]) & I[2])
| (S[1] & S[0] & I[3]);

endmodule
Verilog code to realize 4:1 MUX in dataflow modeling using
conditional operator

module 4t1mux(y, S1, S0, I0, I1, I2, I3);

input S1, S0, I0, I1, I2, I3;

output y;

assign y = S1 ? (S0 ? I3 : I2 ) : (S0 ? I1 : I0);

endmodule
Verilog code to realize 4:1 MUX in behavioral modeling using case
statement

module 4t1mux(input[3:0]I, input[1:0]S, output reg y);

always @(I, S)
begin
case (S)
2’b00 : y = I[0];
2’b01 : Y = I[1];
2’b10 : y = I[2];
2’b11 : y = I[3];
endcase
end
endmodule
Verilog code to realize n:1 MUX in behavioral modeling
module nt1mux(in, sel, y);
parameter m=8;
parameter n=3;

input[m-1:0] in;
input[n-1:0] sel;
output reg y;
integer I;
always @(*)
begin
y=1’b0;
for(i=0;i<m;i=i+1)
begin
if (sel==i) y == in[i];
end
end
endmodule
Verilog code to realize 1:4 dMUX in behavioral modeling using case
statement

module 1t4dmux(input i, input[1:0]s, output reg[3:0] y);

always @(i, s)
begin
y=0;
case (s)
2’b00 : y[0] = i;
2’b01 : Y[1] = i;
2’b10 : y[2] = i;
2’b11 : y[3] = i;
endcase
end
endmodule
Verilog code to realize 1:4 dMUX in behavioral modeling

module 1t4dmux(input i, input[1:0]s, output reg[3:0] y);

always @(i, s)
begin
y[0] = (~s[0]) & (~s[1]) & i;
y[0] = (~s[0]) & (s[1]) & i;
y[0] = (s[0]) & (~s[1]) & i;
y[0] = (s[0]) & (s[1]) & i;
end
endmodule
Verilog code to realize 2 to 4 line decoder in dataflow modeling

module 2t4_decoder (input[1:0] x, output[3:0] y);

assign y[0] = (~x[0]) & (~x[1]);

assign y[1] = (~x[0]) & (x[1]);
assign y[2] = (x[0]) & (~x[1]);
assign y[3] = (x[0]) & (x[1]);

endmodule
Verilog code to realize 3 to 8 line decoder in behavioral modeling
Using case statement
module 3t8_decoder(input[2:0] x, output reg[7:0] y);

always @(x)
begin
case (x)
3’b000 : y[0] = 1;
3’b001 : Y[1] = 1;
3’b010 : y[2] = 1;
3’b011 : y[3] = 1;
3’b100 : y[4] = 1;
3’b101 : y[5] = 1;
3’b110 : y[6] = 1;
3’b111 : y[7] = 1;
endcase
end
endmodule
Verilog code to realize 3 to 8 line decoder in behavioral modeling
Using if-else statement
module 3t8_decoder(input[2:0] x, output reg[7:0] y);

always @(x)
begin
if (x == 3’b000) y = 8’b00000001;
else if (x == 3’b001) y = 8’b00000010;
else if (x == 3’b010) y = 8’b00000100;
else if (x == 3’b011) y = 8’b00001000;
else if (x == 3’b100) y = 8’b00010000;
else if (x == 3’b101) y = 8’b00100000;
else if (x == 3’b110) y = 8’b01000000;
else if (x == 3’b111) y = 8’b10000000;
end
endmodule
Verilog code to realize 8 to 3 line encoder in behavioral modeling
Without priority
module 8t3_encoder(input[7:0] x, output reg[2:0] y);

always @(x)
begin
y[0] = x[7] | x[5] | x[3] | x[1];
y[1] = x[7] | x[6] | x[3] | x[2];
y[2] = x[7] | x[6] | x[5] | x[4];

end
endmodule

B2 = D4 + D5 + D6 + D7; B1 = D2 + D3 + D6 + D7; B0 = D1 + D3 + D5 + D7
Verilog code to realize 8 to 3 line encoder in behavioral modeling
With priority using case statement
module 8t3_encoder(input[7:0] x, output reg[2:0] y);

always @(x)
begin
case (x)
8’b1xxxxxxx : y = 3’b111;
8’b01xxxxxx : Y = 3’b110;
8’b001xxxxx : y = 3’b101;
3’b0001xxxx : y = 3’b100;
3’b00001xxx : y = 3’b011;
3’b000001xx : y = 3’b010;
3’b0000001x : y = 3’b001;
3’b00000001 : y = 3’b000;
endcase
end
endmodule