Scribd
Upload
8 views

Mp Session 4

Uploaded by

Sunil Kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
8 views

Mp Session 4

Uploaded by

Sunil Kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 16

Unit-4

(Instruction Set for IA-32 Platform): Data transfer


instructions, Data processing Instructions, Control
Instructions, A sample Assembly Program
Data transfer instructions
ldw The ldw and stw instructions load and store 32-bit data words from/to
stw memory..

ldwio ldwio and stwio instructions load and store 32-bit data words from/to
stwio peripherals without caching and buffering. Access cycles for ldwio and
stwio instructions are guaranteed to occur in instruction order and are
never suppressed.

ldb ldb, ldbu, ldh and ldhu load a byte or half-word from memory to a
ldbu register. ldb and ldh sign-extend the value to 32 bits, and ldbu and ldhu zero-extend
stb the value to 32 bits.stb and sth store byte and half-word values, respectively.
ldh Memory accesses can be cached or buffered to improve performance. To transfer data
ldhu to I/O peripherals, use the io versions of the instructions, described in the following
sth table cell.
ldbio
ldbuio These operations load/store byte and half-word data from/to
stbio
ldhio
peripherals without caching or buffering.
ldhuio
sthio

•MOV: Moves data between registers and memory


•XCHG: Exchanges data between two locations
•PUSH: Places data onto the stack
•POP: Removes data from the stack
•MOVS: Moves a byte
•MOVZ: Moves with zero extend
•MOVS: Moves with sign extend
•LEA: Loads effective address
•CMOVCC: Conditional move
•IN: Copies a byte or word from a specific port to an accumulator
•OUT: An I/O port transfer instruction
•LDS: A special address transfer instruction
A 32-bit data processing instruction is a type of computer instruction that operates on data in
32-bit chunks. The instruction format for 32-bit data processing includes the following
fields:
•Cond: The condition field
•Op: The operation code, which defines the arithmetic and data operations to be performed
•Funct: The function code
•Rn: The first operand register
•Rd: The destination register
•Src2: The second source operand, which can be an immediate or a shifted register
Data processing instructions

The data processing instructions operate on data held in general-purpose registers. Of the two
source operands, one is always a register. The other has two basic forms:
•An immediate value
•A register value, optionally shifted.
If the operand is a shifted register the shift amount can have an immediate value or the value of
another register. Four types of shift can be specified. Most data processing instructions can
perform a shift followed by a logical or arithmetic operation.
Multiply instructions come in two classes:
•Normal, 32-bit result
•Long, 64-bit result variants.
Both types of multiply instruction can optionally perform an accumulate operation.
Data processing instructions to manipulate data within the registers.

Types for Data Processing Instructions


1.Arithmetic instructions
2.Logical instructions
3.Multiply instructions
4.Comparison instructions
5.Move instructions
1.Arithmetic instructions
The arithmetic instructions mainly implement addition and subtraction of 32bit signed
and unsigned values.
Syntax: <instruction>{<Cond>}{s} Rd, Rn,

ADC add with 32-bit values and carry Rd=Rn+N+carry

ADD add two 32-bit values Rd=Rn+N

RSB reverse subtract of two 32-bit values Rd=N-Rn

reverse subtract with carry of two 32-bit


RSC Rd=N-Rn-!(Carry flag)
values

SBC subtract with carry of two 32-bit values Rd=Rn-N-!(Carry flag)

SUB subtract two 322-bit values Rd=Rn-N


This simple subtract instruction subtracts a value stored in
register r2 from a value stored in register r1. The result is
stored in register r0
PRE
r0 = 0x00000000 ; As this register is a register to
hold the output, that’s why it is empty before execution
r1 = 0x000000002 ; register r1 holds the value ‘2’
r2 = 0x000000001 ; r2 holds another value ‘1’
SUB r0, r1, r2 ; r0=r1 – r2. Here the subtracted
value (r0 – r1) is moved to r0 after performing operation.
POST
r0 = 0x00000001 ; This is the output of above
instruction moved to r0 register
Logical Instruction
Logical instructions perform bitwise logical operations on the two source registers.

Syntax: <instruction>{<cond>} {S} Rd, Rn, N

AND logical bitwise AND of two 32-bit values Rd = Rn & N

ORR logical bitwise OR of two 32-bit values Rd = Rn | N

EOR logical exclusive OR of two 32-bit values Rd = Rn ^ N

BIC logical bit clear (AND NOT) Rd = Rn &~ N


Multiply Instruction
The multiply instructions multiply the contents of a pair of registers depending upon the
instruction, and accumulate the result along with another register . The long multiplies
accumulate onto a pair of registers representing a 64-bit value. The final result is placed on a
destination register or pair of registers.
Syntax – MLA{<Cond>}{S} Rd, Rm, Rs, Rn MUL{<Cond>}{S} Rd, Rm, Rs

MLA Multiply and accumulate Rd = (Rm * Rs) + Rn

MUL multiply Rd = Rm * Rs

[RdHi, RdLo] = [RdHi, RdLo] +


SMLAL signed multiply accumulate long (Rm * Rs)

SMULL signed multiply long [RdHi, RdLo] = Rm * Rs

UMLAL unsigned multiply accumulate long [RdHi, RdLo] = [RdHi, RdLo] +


(Rm * Rs)

UMULL unsigned multiply long [RdHi, RdLo] = Rm * Rs


PRE
r0 = 0x00000000 ; register to hold the output
r1 = 0x00000002 ; register holding the operand 1 value
r2 = 0x00000002 ; register holding the operand 2 value
MUL r0, r1, r2 ; r0 = r1 * r2
POST
r0 = 0x00000004 ; output of the multiplication operation
r1 = 0x00000002
r2 = 0x00000002 ; operands
The UMULL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers
and places the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the result in RdHi.

The UMLAL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers,
and adds the 64-bit result to the 64-bit unsigned integer contained in RdHi and RdLo.

The SMULL instruction interprets the values from Rn and Rm as two's complement signed integers. It multiplies
these integers and places the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the
result in RdHi.

The SMLAL instruction interprets the values from Rn and Rm as two's complement signed integers. It multiplies
these integers, and adds the 64-bit result to the 64-bit signed integer contained in RdHi and RdLo.
Comparison Instructions –
These instructions are used to compare or test a register with a 32-bit value. They update the
cpsr flag bits according to the result, but do not affect other registers. After the bits have been
set, the information can then be used to change program flow by using conditional execution.
Syntax – <instruction>{<cond>} Rn, N

CMN compare negated flags set as a result of Rn + N

CMP compare flags set as a result of Rn – N

TEQ test for quality of two 32 – bit values flags set as a result of Rn ^ N

TST test bits of a 32-bit value flags set as a result of Rn & N


Move Instructions –
Move is the simplest ARM instruction. It copies N into a destination register Rd, where N is a
register or immediate value. This instruction is useful for setting initial values and
transferring data between registers.
Syntax – <instruction>{<cond>}{S} Rd, N

MOV Move a 32-bit value into a register Rd = N

MVN move the NOT of the 32-bit value into a register Rd = ~N

PRE
r5 = 5 ; register value
r7 = 8 ; register value
MOV r7, r5 ;let r7 = r5
POST
r5 = 5 ; data in the register after moving
the r5 data into r7
r7 = 5 ; output after move operation

You might also like