ECE 370

Crystal Structures
 Table 1-1
Common semiconductor materials: (a) the portion of the periodic table
where semiconductors occur; (b) elemental and compound
semiconductors.

Solid State Electronic Devices, Seventh Edition Copyright ©2015, 2006 by Pearson Education, Inc.
Ben G. Streetman | Sanjay Kumar Banerjee All rights reserved.
Figure 1-1 Three types of solids, classified according to atomic arrangement: (a) crystalline and (b) amorphous materials are illustrated by
microscopic views of the atoms, whereas (c) polycrystalline structure is illustrated by a more macroscopic view of adjacent single-
crystalline regions, such as (a).

Solid State Electronic Devices, Seventh Edition Copyright ©2015, 2006 by Pearson Education, Inc.
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Crystalline
Materials
add thermal energy ET 
separation r oscillates
about eq’m spacing r0
Figure 1–2 A two-dimensional lattice showing translation of a unit cell by r = 3a + 2b.

Solid State Electronic Devices, Seventh Edition Copyright ©2015, 2006 by Pearson Education, Inc.
Ben G. Streetman | Sanjay Kumar Banerjee All rights reserved.
Figure 1–4 Packing of hard spheres in an fcc lattice.

Solid State Electronic Devices, Seventh Edition Copyright ©2015, 2006 by Pearson Education, Inc.
Ben G. Streetman | Sanjay Kumar Banerjee All rights reserved.
Figure 1–6 Equivalence of the cube faces ({100} planes) by rotation of the unit cell within the cubic lattice.

Solid State Electronic Devices, Seventh Edition Copyright ©2015, 2006 by Pearson Education, Inc.
Ben G. Streetman | Sanjay Kumar Banerjee All rights reserved.
Figure 1–7 Crystal directions in the cubic lattice.

Solid State Electronic Devices, Seventh Edition Copyright ©2015, 2006 by Pearson Education, Inc.
Ben G. Streetman | Sanjay Kumar Banerjee All rights reserved.
Figure 1–3 Unit cells for three types of cubic lattice structures.

Solid State Electronic Devices, Seventh Edition Copyright ©2015, 2006 by Pearson Education, Inc.
Ben G. Streetman | Sanjay Kumar Banerjee All rights reserved.
Figure 1–8 Diamond lattice structure: (a) a unit cell of the diamond lattice constructed by placing atoms 1/4, 1/4, 1/4 from each atom in an fcc; (b) top
view (along any <100> direction) of an extended diamond lattice. The colored circles indicate one fcc sublattice and the black circles indicate the
interpenetrating fcc.

Solid State Electronic Devices, Seventh Edition Copyright ©2015, 2006 by Pearson Education, Inc.
Ben G. Streetman | Sanjay Kumar Banerjee All rights reserved.
Figure 1–9 Diamond lattice unit cell, showing the four nearest neighbor structure.
(From Electrons and Holes in Semiconductors by W. Shockley, © 1950 by Litton Educational Publishing Co., Inc.; by permission of Van Nostrand Reinhold
Co., Inc.)

Solid State Electronic Devices, Seventh Edition Copyright ©2015, 2006 by Pearson Education, Inc.
Ben G. Streetman | Sanjay Kumar Banerjee All rights reserved.
Figure 1–13 Relationship between band gap and lattice constant for alloys in the InGaAsP and AlGaAsSb
systems. The dashed vertical lines show the lattice constants for the commercially available binary substrates
GaAs and InP. For the marked example of Inx Ga1–x As, the ternary composition x = 0.53 can be grown lattice-
matched on InP, since the lattice constants are the same. For quaternary alloys, the compositions on both the III
and V sublattices can be varied to grow lattice-matched epitaxial layers along the dashed vertical lines between
curves. For example, Inx Ga1–x AsyP1–y can be grown on InP substrates, with resulting band gaps ranging from
0.75eV to 1.35eV. In using this figure, assume the lattice constant a of a ternary alloy varies linearly with the
composition x.

Solid State Electronic Devices, Seventh Edition Copyright ©2015, 2006 by Pearson Education, Inc.
Ben G. Streetman | Sanjay Kumar Banerjee All rights reserved.
Figure 1–10a Pulling of a Si crystal from the melt (Czochralski method): schematic diagram of the crystal growth process.

Solid State Electronic Devices, Seventh Edition Copyright ©2015, 2006 by Pearson Education, Inc.
Ben G. Streetman | Sanjay Kumar Banerjee All rights reserved.
Figure 1–10b Pulling of a Si crystal from the melt (Czochralski method): an 8-in. diameter, <100> oriented Si crystal being pulled from the melt.
(Photograph courtesy of MEMC Electronics Intl.)

Solid State Electronic Devices, Seventh Edition Copyright ©2015, 2006 by Pearson Education, Inc.
Ben G. Streetman | Sanjay Kumar Banerjee All rights reserved.
Figure 1–11a Silicon crystal grown by the Czochralski method. This large single-crystal ingot provides 300 mm (12-in.) diameter wafers when sliced
using a saw. The ingot is about 1.0 m long (including the tapered regions), and weighs about 140 kg. (Photograph courtesy of MEMC Electronics Intl.)

Solid State Electronic Devices, Seventh Edition Copyright ©2015, 2006 by Pearson Education, Inc.
Ben G. Streetman | Sanjay Kumar Banerjee All rights reserved.
Figure 1–11b A technician holding a cassette of 300 mm wafers. (Photographs courtesy of MEMC Electronics Intl.)

Solid State Electronic Devices, Seventh Edition Copyright ©2015, 2006 by Pearson Education, Inc.
Ben G. Streetman | Sanjay Kumar Banerjee All rights reserved.
Figure 1–12 Steps involved in manufacturing Si wafers. (Photograph courtesy of MEMC Electronics Intl.)

Solid State Electronic Devices, Seventh Edition Copyright ©2015, 2006 by Pearson Education, Inc.
Ben G. Streetman | Sanjay Kumar Banerjee All rights reserved.
Figure 1–14 Heteroepitaxy and misfit dislocations. For example, in heteroepitaxy of a SiGe layer on Si, the lattice mismatch between SiGe and Si leads
to compressive strain in the SiGe layer. The amount of strain depends on the mole fraction of Ge. (a) For layer thicknesses less than the critical layer
thickness, tc , pseudomorphic growth occurs. (b) However, above tc , misfit dislocations form at the interface which may reduce the usefulness of the
layers in device applications.

Solid State Electronic Devices, Seventh Edition Copyright ©2015, 2006 by Pearson Education, Inc.
Ben G. Streetman | Sanjay Kumar Banerjee All rights reserved.
Figure 1–16a Crystal growth by molecular beam epitaxy (MBE): evaporation cells inside a high-vacuum chamber directing beams of Al, Ga, As, and
dopants onto a GaAs substrate.

Solid State Electronic Devices, Seventh Edition Copyright ©2015, 2006 by Pearson Education, Inc.
Ben G. Streetman | Sanjay Kumar Banerjee All rights reserved.
Figure 1–16b Crystal growth by molecular beam epitaxy (MBE): scanning electron micrograph of the cross section of an MBE-grown crystal having
alternating layers of GaAs (dark lines) and AlGaAs (light lines). Each layer is four monolayers (4 x α/2 = 11.3 Å;) thick.
(Photograph courtesy of Bell Laboratories.)

Solid State Electronic Devices, Seventh Edition Copyright ©2015, 2006 by Pearson Education, Inc.
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Figure 1–17 Molecular beam epitaxy facility in the Microelectronics Research Center at the University of Texas at Austin.

Solid State Electronic Devices, Seventh Edition Copyright ©2015, 2006 by Pearson Education, Inc.
Ben G. Streetman | Sanjay Kumar Banerjee All rights reserved.