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Class19-1

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Birendra Bhandari
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3 views

Class19-1

Uploaded by

Birendra Bhandari
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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The 8086 Microprocessor

• 16 bit Microprocessor (its internal registers, and most of


its instructions are designed to work with 16-bit binary words )
• It has a 16-bit data bus,( so it can read data from or write
data to memory and ports either 16-bits or 8-bits at a time).
• It has a 20-bit address bus, (so it can address any one
of 220(=1,048,576) memory location).
• Each memory location can hold 8-bit data. (Hence
for 16-bit word, we need two consecutive memory location).
• If the first byte of a word is at an even address: the
8086 can read the entire work in one operation.
• If the first byte of the word is at an odd address: the
8086 will read the first byte with one bus operation
and the second byte with another bus operation.
• The Intel 80186 is an improved version of the 8086.
• The program written for an 8086 is upward-
compatible to an 80186.
• On the other hand, 80186 is also having backward-
compatibility to the 8086 but having some limitation.
• The frequency range of 8086 is 6-10 MHz.
The 8086 Block Diagram
• The 8086 microprocessor is divided into two independent
functional parts:
– The execution unit (EU) ; deals with fetching, decoding and
executing the instructions.
– The bus interface unit (BIU) ; handles all transfers of data
addresses on the buses for execution unit.
• The 8085 has 8 general purpose registers; labeled as AH,
AL, BH, BL, CH, CL, DH, DL can store8-bit data. They can be
used as register pair as Ax, Bx, Cx, and Dx for 16-bit data.
• There are two pointer register:
– Stack Pointer SP
– Base Pointer BP
• There are two index register:
– Source Index
– Destination Index
The 8086 flag register (nine active flag)
The new feature:
• The new feature of 8086 is the use of queue to
provide instruction pipelining.
• While the EU is decoding an instruction or
executing an instruction which does not require
use of the buses, the BIU fetches up to six
instruction bytes for the following instruction.
• The BIU stores these pre-fetched bytes of
instructions in a FIFO register set called a Queue.
• When the EU is ready for its next instruction, it
simply reads the instruction from the queue.
The new feature (2)
• The 8086 BIU sends out 20-bit address, so it can
address any of 220 or 1,048,576 byte of memory.
• However at any given time the 8086 works with
only four 65,536 (64KB) segments with this 1MB
range.
• The four segments are:
• Extra Segment (ES)
• Code Segment (CS)
• Stack Segment(SS)
• Data Segment(DS)
• Instruction Pointer (IP): The instruction pointer
register holds the 16 bit address of the next code
byte (instruction byte) with the code segment.
• Stack Pointer (SP): The stack pointer (SP) register
holds the 16-bit address of the memory location
of the most recently data stored on the stack.
• There are 2 16-bit index register:
• Source Index (SI)
• Destination (DI)

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