Bab 9

Rangkaian
Kombinasional
(Rangkaian Aritmatika)

Oleh Dosen S1 Teknik Elektro

Half Adder

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Unsigned Addition
cont’d…
X = x4x3x2x1x0 0 1 1 1 1 (15)10
+ Y = y 4y3y2y1y0 01010
(10)10 Generated carries
1 1 10 (c3c2c1c0)
S = s 4 s3 s2 s1 s0 1 1 0 0 1 (25)10

B&V: Figure 5.3. An example of addition.

Example of “bit slice” design (full 2n row truth table impractical)

Consider addition of xn and yn

NEED: circuit that takes xn yn and cn to produce sn and cn+1
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Unsigned Addition cont’d…
Full Adder
ci xi yi ci+1 si xiyi
ci 00 01 11 10 xi
0 0 0 0 0
0 0 1 0 1 0 1 1 yi si
0 1 0 0 1
0 1 1 1 0 1 1 1 ci
1 0 0 0 1
1 0 1 1 0 si = xi  yi  ci
1 1 0 1 0
1 1 1 1 1 xiyi
ci 00 01 11 10
ci+1
(a) Truth table 0 1

1 1 1 1

ci+1 = xiyi+ xici+ yici

(b) Karnaugh maps (c) Circuit

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Ripple-Carry Adder
• Naïve implementation of addition us-
ingx full
y
adders. x y x y
n –1 n– 1 1 1 0 0

c1
cn FA cn - 1 c2 FA FA c0

sn – 1 s1 s0
MSB position LSB position

Figure 5.6. An n-bit ripple-carry adder.

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2’s complement
Adder/Subtractor yn – 1 y1 y0

Add /Sub
control

xn – 1 x1 x0

cn n-bit adder c0

sn – 1 s1 s0

Figure 5.13. Adder/subtractor unit.

• xor yi with 1 => 1’s complement; set carry in to add 1

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Multiplexers
• Chooses ONE input based upon select signal.
s
w1 s f
0
1 f 0 w1
w2 1 w2
(a) Graphical symbol (b) Truth table

w1
s f
w2

(c) Sum-of-products circuit

A 2-to-1 multiplexer (B&V: Figure 6.1)

May 11, 2006 EECE 353/379 7

 A 4-to-1 multiplexer
(B&V: Figure 6.2)
s0
s1
w0 00
s0
w1 01
w2 f w0
10
w3 11 s1

(a) Graphic symbol w1

f
s1 s0 f
w2
0 0 w0
0 1 w1
1 0 w2
1 1 w3 w3

(b) Truth table

(c) Circuit

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Implementation
s1
s0

w0 0
w1 1

0
f
1

w2 0
w3 1

Using 2-to-1 multiplexers to build a 4-to-1

multiplexer (B&V: Figure 6.3)

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 Synthesis of Logic Functions with Multiplexers

Example: XOR function f = w1  w2

w1 w2 f f
w1
w2 0 0 0 w2
w1 w2 f 0
w1 0 1 1
1 w2
0 0 0 1 0 1
0
0 1 1 1 1 1 0
1 0 1 f
1
1 1 0 0 (b) Modified truth table

(a) Implementation using a 4-to-1 multiplexer w1

w2
f

(c) Circuit

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 Example: Majority
Function
w1 w2 w3 f
w1 w2 f
0 0 0 0
0 0 0
0 0 1 0 w3
0 1 w2
0 1 0 0 w3 w1
1 0
0 1 1 1 1 1 1
1 0 0 0 0
w3
1 0 1 1 (a) Modified truth f
1 1 0 1 table 1
1 1 1 1 (b) Circuit

Implementation of the three-input majority function using a

4-to-1 multiplexer (B&V: Figure 6.8)

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Example: 3-input XOR
function
w1 w2 w3 f

0 0 0 0
w3
0 0 1 1 w2
0 1 0 1 w1
w3
0 1 1 0 w3
1 0 0 1 f
w3
1 0 1 0
1 1 0 0
w3
1 1 1 1

(a) Truth table (b) Circuit

B&V: Figure 6.10.

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Decoders
• n bits => 2n possible combinations of 1’s
and 0’s
• Decoder : asserts ONE out of 2n output
signals to indicate which combination of
1’s and 0’s is on the input (output is “one
hot encoded”)
w0 y0
n
inputs 2n
wn – 1 outputs
y2n – 1
Enable En
An n-to-2n binary decoder (B&V: Figure 6.15)

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Decoder Implementation
w0
y0
w1
En w1 w0 y0 y1 y2 y3

1 0 0 1 0 0 0 y1
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
0 x x 0 0 0 0 y2

(a) Truth table

y3

En

(c) Logic circuit

• En = 0 => all outputs (y0… y3) are

zero 14
Decoder Tree
w0 w0 y0 y0
w1 w1 y1 y1
y2 y2
En y3 y3

w0 y0 y4
w1 y1 y5
y2 y6
w2 w0 y0 y3 y7
En
w3 w1 y1
y2
En En y3 w0 y0 y8
w1 y1 y9
y2 y10
En y3 y11

w0 y0 y12
w1 y1 y13
y2 y14
En y3 y15

A 4-to-16 decoder built using a decoder tree (B&V: Figure 6.18)

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What are they good for?
Example:

m-to-2m decoder
Sel0
0/1 0/1 0/1

Sel1

Memory a0 Sel2
0/1 0/1 0/1

0/1 0/1 0/1

Address a1

am – 1

Sel2m – 1
0/1 0/1 0/1

Read

Data dn – 1 dn – 2 d0

A 2m x n read-only memory (ROM) block (B&V: Figure 6.21)

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Demultiplexer
• Inverse operation of a Multiplexer: Take 1 input, and
output it to one of m=2n outputs.
• Can implement using a Decoder

w0 y0
n-bit
selec 2n
t wn – 1 outputs

x y2n – 1
En
ys = x
(where s = wn-1wn-2…w0 in binary)
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Encoders
• Performs the opposite operation of a decoder (!)
• Input = “one hot encoding”
• Output = binary representation of the “index” of the
wire that is “hot” (equal to 1)

w0
y0
2n n
inputs outputs
yn – 1
w2n – 1

A 2n-to-n binary encoder (B&V: Figure 6.22)

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Encoder Implementation
w0
w3 w2 w1 w0 y1 y0
w1
0 0 0 1 0 0 y0
0 0 1 0 0 1
w2
0 1 0 0 1 0
1 0 0 0 1 1 y1
w3

(a) Truth table (b) Circuit

(note: truth table ignores “impossible” input patterns… treats outputs as

“don’t care” conditions for purposes of logic optimization, e.g., using K-
maps)
A 4-to-2 binary encoder (B&V: Figure 6.23).

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BCD To 7-Segment
w3 w2 w1 w0 a b c d e f g

a a 0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
w0 b
c f b 0 0 1 0 1 1 0 1 1 0 1
w1 0 0 1 1 1 1 1 1 0 0 1
w2 d g
e e c 0 1 0 0 0 1 1 0 0 1 1
w3 0 1 0 1 1 0 1 1 0 1 1
f
g d 0 1 1 0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
(a) Code converter (b) 7-segment display 1 0 0 1 1 1 1 1 0 1 1

(c) Truth table

A BCD-to-7-segment display code converter (B&V: Figure 6.25)

• NOTE: “abcdefg” in figure above are different than in

Lab 1! (see lab hand out on course website for correct
definition)

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